Patents by Inventor Chris Haywood
Chris Haywood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9984027Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.Type: GrantFiled: January 29, 2016Date of Patent: May 29, 2018Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood, Thomas Reiner, Ken Wong
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Patent number: 9841806Abstract: A memory load sharing system and method therefor. This system can include a platform VRM (Voltage Regulator Module) coupled to a memory channel with the platform VRM having a platform voltage input. One or more first memory modules can coupled to the platform VRM through the memory channel. Each of the first memory modules includes one or more plane connectors and a module connector, as well as a memory module VRM coupled to a module load sharing diode that is coupled to the one or more plane connectors of that first memory module. The platform VRM is coupled to a first platform load sharing diode that is coupled the plane connectors of each of the first memory modules. This platform is configured to support load sharing between the first memory modules and to provide a predetermined amount of power to each of the memory modules.Type: GrantFiled: May 7, 2015Date of Patent: December 12, 2017Assignee: Rambus Inc.Inventor: Chris Haywood
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Publication number: 20160147693Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.Type: ApplicationFiled: January 29, 2016Publication date: May 26, 2016Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood, Thomas Reiner, Ken Wong
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Patent number: 7990987Abstract: A network processor having bypass capability in which some data units are diverted from being processed by the processor core of the network processor. In one embodiment, a network processor may include a receiver to receive data units, configuration information used to evaluate whether the data units require processing, a processor core to process data units that require processing, a bypass store to hold those data units which do not require processing by the processor core, and a transmitter to transmit the data units. In one embodiment, a method may include receiving a plurality of data units, receiving configuration information, evaluating whether each of the data units requires processing based on the configuration information, bypassing processing those of the data units that do not require processing based on the evaluating, processing those of the data units that require processing based on the evaluating, and transmitting the data units.Type: GrantFiled: February 25, 2003Date of Patent: August 2, 2011Assignee: Topside Research, LLCInventors: Thomas C Reiner, Kirk Jong, Phil Terry, Neely Walls, Chris Haywood, Michael de la Garrigue, Adam Rappoport
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Patent number: 7945722Abstract: Methods for routing data units and PCI Express switches are disclosed. A plurality of devices may be coupled to a corresponding plurality of physical interfaces, each physical interface having a respective configurable status and a respective address domain, wherein in a first status the interface is transparent, and in a second status the interface is non-transparent. The status of each of the plurality of physical interfaces may be set as transparent or non-transparent. Data units may be switched between the physical interfaces using mapped address input/output, switching data units including masking the address domain for the interfaces configured as non-transparent.Type: GrantFiled: September 29, 2010Date of Patent: May 17, 2011Assignee: Internet Machines, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Publication number: 20110016258Abstract: Methods for routing data units and PCI Express switches are disclosed. A plurality of devices may be coupled to a corresponding plurality of physical interfaces, each physical interface having a respective configurable status and a respective address domain, wherein in a first status the interface is transparent, and in a second status the interface is non-transparent. The status of each of the plurality of physical interfaces may be set as transparent or non-transparent. Data units may be switched between the physical interfaces using mapped address input/output, switching data units including masking the address domain for the interfaces configured as non-transparent.Type: ApplicationFiled: September 29, 2010Publication date: January 20, 2011Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Patent number: 7814259Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.Type: GrantFiled: August 20, 2008Date of Patent: October 12, 2010Assignee: Internet Machines, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Patent number: 7639707Abstract: A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.Type: GrantFiled: September 27, 2005Date of Patent: December 29, 2009Inventor: Chris Haywood
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Patent number: 7590791Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.Type: GrantFiled: August 21, 2008Date of Patent: September 15, 2009Assignee: Topside Research, LLCInventors: Heath Stewart, Chris Haywood, Michael De La Garrigue, Nadim Shaikli, Ken Wong, Bao Vuong, Thomas Reiner, Adam Rappoport
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Publication number: 20090228568Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.Type: ApplicationFiled: May 19, 2009Publication date: September 10, 2009Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood, Thomas Reiner, Ken Wong
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Patent number: 7539190Abstract: There is disclosed apparatus and methods of multicasting in a shared address space. There may be defined a number of portions of the address space. There may be groups of the portions, and data units addressed to one portion within the group may be re-addressed to the other portions.Type: GrantFiled: February 13, 2004Date of Patent: May 26, 2009Assignee: Topside Research, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood, Thomas Reiner, Ken Wong
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Publication number: 20080307150Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.Type: ApplicationFiled: August 21, 2008Publication date: December 11, 2008Inventors: Heath Stewart, Chris Haywood, Mike De la Garrigue, Nadim Shaikli, Ken Wong, Bao Vuong, Thomas Reiner, Adam Rappoport
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Publication number: 20080304504Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.Type: ApplicationFiled: August 20, 2008Publication date: December 11, 2008Inventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Patent number: 7454552Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.Type: GrantFiled: November 18, 2004Date of Patent: November 18, 2008Assignee: Topside Research, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Patent number: 7426602Abstract: There is disclosed a bus optimization technique. Pursuant to the bus optimization technique, the output buffer and output logic are removed from port units of a switch and are included with a control matrix in the switch. Data units received in a first port unit of a plurality of port units are provided to a control matrix. The control matrix evaluates when to send the data unit to a second port unit. No output decisions are made in the second port unit.Type: GrantFiled: January 7, 2005Date of Patent: September 16, 2008Assignee: Topside Research, LLCInventors: Heath Stewart, Chris Haywood, Mike de la Garrigue, Nadim Shaikli, Ken Wong, Bao Vuong, Thomas Reiner, Adam Rappoport
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Patent number: 7421532Abstract: There are disclosed apparatus and methods for switching. Transparent and non-transparent ports are provided. Data units are transferred between the transparent ports, between the transparent and non-transparent ports, and between the non-transparent ports.Type: GrantFiled: January 6, 2005Date of Patent: September 2, 2008Assignee: Topside Research, LLCInventors: Heath Stewart, Michael de la Garrigue, Chris Haywood
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Publication number: 20060072598Abstract: A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.Type: ApplicationFiled: September 27, 2005Publication date: April 6, 2006Inventor: Chris Haywood
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Patent number: 6987775Abstract: A variable size first in first out (FIFO) memory is provided. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.Type: GrantFiled: August 15, 2001Date of Patent: January 17, 2006Assignee: Internet Machines Corp.Inventor: Chris Haywood
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Publication number: 20050265357Abstract: There are disclosed apparatus and methods for achieving maximum data transfer. Memories and interfaces between the memories are provided. An actively determined number of data units having an actively determined unit size are transferred between the memories to provide the maximum data transfer.Type: ApplicationFiled: August 11, 2005Publication date: December 1, 2005Inventor: Chris Haywood
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Patent number: 6941426Abstract: A head and tail caching system. The system includes a tail FIFO memory having a tail input to receive incoming data. A memory is included that is operable to store data that is output from the tail FIFO and output the stored data at a memory output. A multiplexer is included having first and second multiplexer inputs coupled to the tail FIFO and the memory, respectively. The multiplexer has a control input to select one of the multiplexer inputs to coupled to a multiplexer output. A head FIFO memory receives data from the multiplexer output, and outputs the data on an output data path. A controller is operable to transfer one or more blocks data having a selected block size from the tail FIFO to the memory and from the memory to the head FIFO, to achieve a selected efficiency level.Type: GrantFiled: December 31, 2001Date of Patent: September 6, 2005Assignee: Internet Machines Corp.Inventor: Chris Haywood