Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=¼*(f4) causing a coarse frequency adjustment and a signal ?=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: A high-density memory module is made up of two memory boards, each with memory elements affixed to each of two sides, the two memory boards disposed on either side of a central rigid substrate, each memory board having a flexible wiring array, electrically and mechanically affixed at one end to one of the memory board and at the other end to the other of the memory boards, the flexible wiring array wrapped at its midpoint around a bottom of the central rigid substrate, so that two linear arrays of comb tabs affixed to the flexible wiring array are disposed in proximity to the bottom of the central rigid substrate, so that the central rigid substrate may be inserted into a mating electrical connector, making an electrical connection with both memory boards.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=1/4*(f4) causing a coarse frequency adjustment and a signal A=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: A circuit for terminating devices attached to a signal line and driving a load includes a resistor R1 in series with the signal line circuit CR1 having a resistor in series with a switch wherein CR1 is in parallel with R1, a circuit CR2 having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CR3 having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, a circuit CR4 having a resistor in series with a switch, connected at one end to ground and at the other to the load, a circuit CR5 having a resistor in series with a switch, connected at one end to Vcc and at the other to the load, and a capacitor connected between the receiver or transmitter and ground.

Abstract: A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connected to the clock signal, and an output signal s2, an OR circuit having a first input connected to the data input, a second input connected to s2, and an output signal s3, and a FLIP-FLOP circuit whose first input is connected to s2, whose second input connected to s3, and whose output is OUT Q.

Abstract: A high speed bidirectional data rate conversion circuit converts 1× data rate signals from attached devices on port A and port B to 2× data rate signals on bus C and further converts 2× high speed data rate signals on bus C to 1× data rate signals on ports A and B for memory devices attached to ports A and B. The usage of pass gate switches and combination of latches and counters is used to permit proper synchronization of the data signals, and to further generate strobe signals at both system bus and memory bus sides, and to further generate data mask signals for writing to the memory bus side of the circuit. The collection of such switching elements and latches are provided on a single silicon chip which includes of the functions of the invention.

Abstract: A tri-directional, high-speed switching element connects to a bus port, an A memory port, and a B memory port. A first FET switch” source is connected to the bus port, and a second FET switch”s drain is connected to the A memory port, and its source is connected to the first FET switch”s drain. A third FET switch”s drain is connected to the B memory port, and its source is connected to the second FET switch”s drain. This element permits all three ports to be isolated from each other, or for the A and B ports to be interconnected, but isolated from the bus port, or for all ports to be connected together. A collection of 8 such switching elements is provided on a single silicon chip, providing switching for a byte of interleaved memory.

Abstract: A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a first memory bank having data lines and a second memory bank having data lines. The first and second memory banks are associated with first and second clock signals, respectively, where the second clock signal is delayed from the first clock signal such that the data lines of the first memory bank are connected to a data bus in synchronism with the first clock signal while the data lines of the second memory bank are connected with the data bus in synchronism with the second clock signal. In one embodiment, a first FET switch connects the data lines of the first memory bank with the data bus and a second FET switch connects the data lines of the second memory bank with the data bus.

Abstract: A tri-directional, high-speed switching element connects to a bus port, an A memory port, and a B memory port. A first FET switch' source is connected to the bus port, and a second FET switch's drain is connected to the A memory port, and its source is connected to the first FET switch's drain. A third FET switch's drain is connected to the B memory port, and its source is connected to the second FET switch's drain. This element permits all three ports to be isolated from each other, or for the A and B ports to be interconnected, but isolated from the bus port, or for all ports to be connected together. A collection of 8 such switching elements is provided on a single silicon chip, providing switching for a byte of interleaved memory.

Abstract: A flexible asymmetrical jumper assembly is used to electrically join to circuit boards together where the geometry requires that the jumper be bent, often in a tight loop, so that the pads which form the ends of the jumper are parallel to each other. The jumper assembly contains two sets of wires, each set containing an array of foil fingers terminated in pads. The upper set of wires is bonded to the upper side of a central insulating sheet, while the lower set is bonded to the lower side of the central insulating sheet. An upper insulating sheet is bonded to the upper side of the upper set of wires, leaving the pads exposed for later soldering. A lower insulating sheet is likewise bonded to the lower side of the lower set of wires, with the pads also exposed. A hole is drilled through each upper pad, through the center insulating sheet, and into the corresponding lower pad. The holes are then through plated. The pads are of two different types, a major, or larger pad, and a minor, or smaller pad.

Abstract: A low profile, registered DIMM has a height of about 1.2 inches, and a width of about 5.25 inches. This reduced size is accomplished by arranging the SDRAMs into a left group and a right group within a single row, with a space between the groups into which all other major components are disposed. In addition, the pad extensions beyond the SDRAM pins are maintained at about 0.1 mm, the footprints of the pads to accept the SDRAMs are a minimum of 11.76 mm, as measured by the lengthwise distance from the first pad in a footprint to the pad furthest away, and the space between adjacent pads is between 0.127 mm and 0.750 mm.

Abstract: A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches to select a proper termination chip for the computer system bus. The apparatus includes one or more multi-sided termination boards with etched leads, lands and feed-throughs. The termination chips may be mounted on either one side, or both sides of each board. Connection between the termination boards and the mother board are made by means of a comb of contact fingers or edge-connector which mates with a connector on the mother board. The data lines and address lines of the computer bus are distinct from each other, and routed to the termination board via the edge connector. A set of CMOS TTL or FET switches are located adjacent to the comb, and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU, controller or other decoding means located on the motherboard.

Abstract: A method and apparatus for enhancing memory speed and capacity utilizes a set of electronic switches to isolate the computer data bus from the memory chips. The apparatus includes one or more multi-sided memory boards with etched leads, lands and feed-through. The memory chips may be mounted on either one side, or both sides of each board. Connection between the memory board and the mother board are made by means of a comb of contact fingers, or edge-connector which mates with a connector on the mother board. The data lines and address lines of the computer bus are distinct from each other, and routed to the memory board via the edge connector. A set of CMOS TTL or FET switches are located adjacent to the comb, and are switched on and off by a decoded combination of address, control, or data lines or by a distinct enable line provided by the CPU, controller or other decoding means located on the motherboard.

Abstract: An electronic assembly is made up of a number of rigid manufactured on the same or different substrates or panels and with the same materials separated from each other electrically and physically. One of the rigid circuit boards has a comb of printed tabs, or fingers, at the edge, which connects the assembly physically and electrically to a motherboard. Flexible wire jumpers bridges the comb to form electrical connections between the boards. Both boards have printed circuit tabs placed in alignment to each other on both boards across a gap which separates both boards. These tabs facilitate electronic interconnection of both boards via the flexible jumpers, which are groups or clusters of wires separated from each other via a flexible insulator. A method for manufacturing the assembly is also disclosed, in which two boards are created by cutting gaps from a substrate, leaving the two boards separated by a gap and connected by snap-offs.

Abstract: In a header assembly, for interconnecting an electronic module to a mother board, including an insulating strip and at least one row of spaced-apart pins inserted through holes between an upper face and a lower face of the strip, each of the pins having an upper portion projecting from the upper face and being shaped and dimensioned to interconnect with the module, and a lower portion projecting from the lower face and being shaped and dimensioned to interconnect with the mother board, any adjacent two of the pins being separated by a length of the strip, the improvement which includes a plurality of collars of heat-dissipating material, one of the collars mounted around and in intimate contact with each of the pins, the collars having a peripheral outline shaped and dimensioned to avoid electrical contact with an adjacent pin.

Abstract: An electronic assembly combines a number of commensurate printed circuit boards bonded to a common, flexible, interconnecting substrate in an alternately folded and layered arrangement against an end board that has a comb of terminals for mounting into a motherboard connector. The flexible substrate is sandwiched between half-sections of each board, allowing mounting of components from both faces of the board. The assembly is particularly indicated for high density applications such as memory modules.

Abstract: A remote fan out facility used in an information handling system including a plurality of data terminals located remotely from a central processor unit. Messages transmitted from the central processing unit to one of the plurality of data terminals are modified by creating and inserting a terminal device address into the outbound messages. The messages are then transmitted to a fan out box located near the addressed terminal. The fan out box strips the terminal address from the received message, decodes the stripped address, and directs the message to the appropriate data terminal according to the stripped decoded address. By this means, a single serial transmission link can be used to connect the central processing unit to a plurality of data terminals without undue modification of an existing system.

Abstract: An interrupt interface circuit for connection to a shared interrupt request line. An internally generated interrupt impresses an interrupt request line and also locks out any further interrupt requests until the interrupt request is analyzed to be of a minimum duration, in which case the lock out is latched. An interrupt request on the shared interrupt request line is also analyzed for minimum duration before it causes a lock out to be latched. A latched lock out is removed by a signal generated by the interrupt handler.