Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: An approach for determining an infrastructure service interruption is disclosed. The approach relies on utilizing UAVs (unmanned aerial vehicle) to map electronic signals (e.g., Wi-Fi, etc.) that emanates from building structures (e.g., residential, commercial, etc.). Electronic signals having a certain frequency or multiple frequencies may be used. Essentially, the approach can detect power/signal loss by comparing differences in Wi-Fi signal maps pre and post event (e.g., severe thunderstorm, etc.). The 24/7 event monitoring is carried out by using UAVs and the UAVs can operate on a regular or event driven schedule vs. continuously operating multiple fixed data collection units.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: Disclosed are embodiments of forming porous copper on the end of a copper pillar. The embodiments may be used to remove solder from selected locations on a chip or laminate substrate.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.

Abstract: An IC device package includes an IC device that is connected to a lid by a thermal interface material (TIM). A catalyst material is formed upon one or more regions upon an upper surface of the IC device and/or an under surface of the lid. The catalyst material increases the rate of crosslinking of polymer chains of the TIM during TIM curing and/or increases the strength of crosslinks that link polymer chains of the TIM during TIM curing. The catalytically enhanced regions have a higher coefficient of heat transfer relative to non-catalytically enhanced regions. Therefore, the catalytically enhanced regions efficiently transfer heat from the IC device to the lid.

Abstract: Disclosed are embodiments of forming porous copper on the end of a copper pillar. The embodiments may be used to remove solder from selected locations on a chip or laminate substrate.

Abstract: A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

Abstract: A modified socket mechanism comprises a printed circuit board and a connector component located on a first face of the printed circuit board. The modified socket mechanism may comprise a first region of electrical contacts located on the first face. The first region of electrical contacts may be designed to interface with a processor module. The modified socket mechanism may also comprise a second region of electrical contacts located on a second face of the printed circuit board. The second region of electrical contacts may be designed to interface with a motherboard. The modified socket mechanism may also comprise a first electrical connection between the connector component and the first region of electrical contacts through the printed circuit board. Finally, the modified socket mechanism may also comprise a second electrical connection between the first region of electrical contacts and the second region of electrical contacts through the printed circuit board.

Abstract: A modified socket mechanism comprises a printed circuit board and a connector component located on a first face of the printed circuit board. The modified socket mechanism may comprise a first region of electrical contacts located on the first face. The first region of electrical contacts may be designed to interface with a processor module. The modified socket mechanism may also comprise a second region of electrical contacts located on a second face of the printed circuit board. The second region of electrical contacts may be designed to interface with a motherboard. The modified socket mechanism may also comprise a first electrical connection between the connector component and the first region of electrical contacts through the printed circuit board. Finally, the modified socket mechanism may also comprise a second electrical connection between the first region of electrical contacts and the second region of electrical contacts through the printed circuit board.

Abstract: A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

Abstract: A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

Abstract: At least one plating pen is brought into aligned relationship with at least one hole defined in a board. The pen includes a central retractable protrusion, a first shell surrounding the protrusion and defining a first annular channel therewith, and a second shell surrounding the first shell and defining a second annular channel therewith. The protrusion is lowered to block the hole and plating material is flowed down the first channel to a surface of the board and up into the second channel, to form an initial deposit on the board surface. The protrusion is raised to unblock the hole, and plating material is flowed down the first annular channel to side walls of the hole and up into the second annular channel, to deposit the material on the side walls of the hole.