Abstract: In one embodiment, the present invention includes a method for setting an entry in an override register corresponding to a processor feature to override a processor configuration setting for the processor feature and overriding the processor configuration setting for the processor feature using the entry. The entry may be set with a user-level application, for example.

Abstract: A method and apparatus is described herein for monitoring the performance of a microarchitecture and tuning the microarchitecture based on the monitored performance. Performance is monitored through simulation, analytical reasoning, retirement pushout measure, overall execution time, and other methods of determining per instance event costs. Based on the per instance event costs, the microarchitecture and/or the executing software is tuned to enhance performance.

Abstract: Cache coherency rules for a multi-processor computing system that is capable of working with compressed cache lines' worth of information are described. A multi-processor computing system that is capable of working with compressed cache lines' worth of information is also described. The multi-processor computing system includes a plurality of hubs for communicating with various computing system components and for compressing/decompressing cache lines' worth of information. A processor that is capable of labeling cache lines' worth of information in accordance with the cache coherency rules is described. A processor that includes a hub as described above is also described.

Abstract: A memory controller is described that comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information. A processor and a memory controller integrated on a same semiconductor die is also described. The memory controller comprises a compression map cache. The compression map cache is to store information that identifies a cache line's worth of information that has been compressed with another cache line's worth of information.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a plurality of compressible cache lines to store additional data.

Abstract: A method is provided including determining if an object has been published previously, identifying the object as public according to whether the object has been published previously, identifying objects reachable from the object as public according to whether the object has been published previously, and publishing the object. An apparatus for performing the method, and an article including a machine- accessible medium that provides instructions that, if executed by a processor, will cause the processor to perform the method are also provided.

Abstract: Methods and systems are provided to selectively log branch trace store data associated with the execution of an application. A privilege level is received, which identifies an execution mode for a processor for which branch trace store data is to be logged to a buffer. The privilege level is used to set one or more privilege flags that permit selective branch trace store data to be logged in the buffer when the application is executed. In one embodiment, the privilege level represents a user application mode, a supervisory application mode, or a mode representing both a user application mode and a supervisory application mode.