Abstract: Systems, methods, and apparatus managing access to a power management device are disclosed. A system has a primary integrated circuit and a power management integrated circuit. The primary integrated circuit has a communication controller configured to control access to a first serial bus for a plurality of subsystems in the primary integrated circuit. The power management integrated circuit is coupled to the first serial bus and to a second serial bus. An access control circuit in the power management integrated circuit is configured by the primary integrated circuit to control access to the power management integrated circuit through the second serial bus. The primary integrated circuit may be configured to write an access control configuration to the power management integrated circuit. The access control configuration may define write access rights for a secondary integrated circuit coupled to the power management integrated circuit through the second serial bus.

Abstract: A voltage regulator circuit using predictively precharged voltage rails is generally disclosed. For example, the voltage regulator circuit may include a main switching regulator configured to provide a target voltage, the main switching regulator having a first voltage node, a precharge switching regulator configured to provide a precharge voltage, the precharge switching regulator having a second voltage node, the precharge voltage based on a difference between the target voltage and a next target voltage to be provided by the main switching regulator, and a precharge switch circuit configured to selectively couple the second voltage node to an output voltage node based upon a transition from the target voltage to the next target voltage.

Abstract: A voltage regulator circuit using predictively precharged voltage rails is generally disclosed. For example, the voltage regulator circuit may include a main switching regulator configured to provide a target voltage, the main switching regulator having a first voltage node, a precharge switching regulator configured to provide a precharge voltage, the precharge switching regulator having a second voltage node, the precharge voltage based on a difference between the target voltage and a next target voltage to be provided by the main switching regulator, and a precharge switch circuit configured to selectively couple the second voltage node to an output voltage node based upon a transition from the target voltage to the next target voltage.

Abstract: A voltage regulator circuit using precharge voltage rails is generally disclosed. For example, the voltage regulator circuit may include a first voltage regulator having a voltage output, an output capacitor coupled to the voltage output, and one or more precharge voltage circuits configured to selectively couple to the voltage output, each of the one or more precharge voltage circuits comprising a capacitor coupled between an output of a precharge voltage regulator and a reference potential.

Abstract: An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Abstract: Systems and methods are disclosed method for operating a serial interconnect of a computer system in a time deterministic manner. An exemplary method comprises that a command to be sent over the serial interconnect in a transaction is to be executed at a specific time. A delay period for the command to be sent from a master of the computer system to a slave of the computer system via the serial bus is determined, where the delay period determined based on a length of an arbitration phase of the transaction. The command is then sent to the slave of the computer system via the serial bus after the delay period.

Abstract: A voltage regulator circuit using predictively precharged voltage rails is generally disclosed. For example, the voltage regulator circuit may include a main switching regulator configured to provide a target voltage, the main switching regulator having a first voltage node, a precharge switching regulator configured to provide a precharge voltage, the precharge switching regulator having a second voltage node, the precharge voltage based on a difference between the target voltage and a next target voltage to be provided by the main switching regulator, and a precharge switch circuit configured to selectively couple the second voltage node to an output voltage node based upon a transition from the target voltage to the next target voltage.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

Abstract: A voltage regulator circuit using precharge voltage rails is generally disclosed. For example, the voltage regulator circuit may include a first voltage regulator having a voltage output, an output capacitor coupled to the voltage output, and one or more precharge voltage circuits configured to selectively couple to the voltage output, each of the one or more precharge voltage circuits comprising a capacitor coupled between an output of a precharge voltage regulator and a reference potential.

Abstract: Systems and methods are disclosed method for operating a serial interconnect of a computer system in a time deterministic manner. An exemplary method comprises that a command to be sent over the serial interconnect in a transaction is to be executed at a specific time. A delay period for the command to be sent from a master of the computer system to a slave of the computer system via the serial bus is determined, where the delay period determined based on a length of an arbitration phase of the transaction. The command is then sent to the slave of the computer system via the serial bus after the delay period.

Abstract: An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Abstract: Systems and methods are disclosed resetting a slave identification (SID) of an integrated circuit (IC). An exemplary method comprises determining that a plurality of ICs in communication with a shared bus have the same SID, the shared bus operating in a master/slave configuration. A common memory address of the ICs is identified, where data stored in the common memory address is different for a first IC and a second IC. Each of the ICs receives over the shared bus a new SID value and match data. The ICs compare the match data with the data stored in the common memory address. If the match data is the same as the data in the common memory address, the SID is changed the received new SID value.

Abstract: Systems and methods are disclosed resetting a slave identification (SID) of an integrated circuit (IC). An exemplary method comprises determining that a plurality of ICs in communication with a shared bus have the same SID, the shared bus operating in a master/slave configuration. A common memory address of the ICs is identified, where data stored in the common memory address is different for a first IC and a second IC. Each of the ICs receives over the shared bus a new SID value and match data. The ICs compare the match data with the data stored in the common memory address. If the match data is the same as the data in the common memory address, the SID is changed the received new SID value.

Abstract: A circuit comprising an ECM system is provided. The circuit includes a current monitor circuit configured to monitor the ECM system to measure a set of currents supplied to a set of circuits. The circuit also includes an alert circuit configured to generate an alert based on at least one current of the set of currents in comparison to at least one threshold. The circuit further includes a throttle circuit configured to throttle a performance of at least one circuit in order to decrease the current to the at least one circuit based on the generation of the alert. The current used by the circuit may act as an analogue for the system power used. Accordingly, the current used by the circuit may be used to determine when to throttle one or more aspects of the functionality of the circuit.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

Abstract: A circuit comprising an ECM system is provided. The circuit includes a current monitor circuit configured to monitor the ECM system to measure a set of currents supplied to a set of circuits. The circuit also includes an alert circuit configured to generate an alert based on at least one current of the set of currents in comparison to at least one threshold. The circuit further includes a throttle circuit configured to throttle a performance of at least one circuit in order to decrease the current to the at least one circuit based on the generation of the alert. The current used by the circuit may act as an analogue for the system power used. Accordingly, the current used by the circuit may be used to determine when to throttle one or more aspects of the functionality of the circuit.

Abstract: Circuitry configured for dynamically adjusting clock signal quality based on an operating mode for power savings is described. The circuitry includes clock generation circuitry. The circuitry also includes mode control circuitry. The mode control circuitry provides a drive signal based on an operating mode. The circuitry also includes clock buffer circuitry coupled to the clock generation circuitry and to the mode control circuitry. The clock buffer circuitry adjusts a clock signal quality based on the drive signal.