Abstract: An amplifier is described which amplifies an input signal according to a defined amplification factor, and which generates an output signal. To reduce an offset fraction of the output signal the amplifier comprises a feedback path which has lowpass characteristics and which returns the output signal in a lowpass-filtered state to an input of the amplifier. The feedback path comprises an amplifier stage as well as at least one Miller capacitance connected between an input and an output of the amplifier stage.

Abstract: It is an object of the present invention to provide an amplifier circuit that supplies a differential output signal (Voutp?Voutn) with a stable common mode potential (½×(Voutp+Voutn)) and a stable amplification characteristic. An essential feature of the invention is a control path (24, 26, 30, 28, 36, 38, 34, 32) feeding back into a control stage of the amplifier circuit for the combined control of the quiescent currents that flow through the output transistors (T1-T4), and of the common mode potential of the differential output signal. By means of this combination of two control functions in one and the same control path (24, 26, 30, 28, 36, 38, 34, 32) any coupling between separate control loops is avoided.

Abstract: A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.

Abstract: The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).

Abstract: The invention relates to a continuous-time delta-sigma analog digital converter (10) for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (20), which filters the analog input signal, a quantifier (30) cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter (20) to generate the digital output signal, and a feedback device (40) with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (20).

Abstract: The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK<1:8>). The sampling (14) delivers a first, more significant digital component (OUT1<9:0>) of the phase detection signal (PD_OUT).

Abstract: It is an object of the present invention to provide an amplifier circuit that supplies a differential output signal (Voutp-Voutn) with a stable common mode potential (½×(Voutp+Voutn)) and a stable amplification characteristic. An essential feature of the invention is a control path (24, 26, 30, 28, 36, 38, 34, 32) feeding back into a control stage of the amplifier circuit for the combined control of the quiescent currents that flow through the output transistors (T1-T4), and of the common mode potential of the differential output signal. By means of this combination of two control functions in one and the same control path (24, 26, 30, 28, 36, 38, 34, 32) any coupling between separate control loops is avoided.

Abstract: The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s1, s2, s1*, s2*), which have the specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel switching of adjustable transconductance stages which are each adjusted by the control signal (x) and to each of which one of the input signals (s1, s2, s1*, s2*) is supplied.

Abstract: A test method and a test device for testing an integrated circuit are configured to allow for a test device which dispenses with the hardware provision of the boundary scan cells in the device. For this purpose, the boundary scan cells are reproduced by way of a boundary scan program. All functionalities of the chain of boundary scan cells and the TAP interface are fulfilled by the use of the boundary scan program, which is executed by a program-controlled control device that is controlled by the integrated circuit.

Abstract: The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).

Abstract: The invention relates to a continuous-time delta-sigma analog digital converter (10) for converting an analog input signal (IN) to a digital output signal (OUT), comprising an analog filter (20), which filters the analog input signal, a quantifier (30) cycled by a clock signal (CLK), which quantifier quantifies the filtered analog signal transmitted by the analog filter (20) to generate the digital output signal, and a feedback device (40) with at last one digital analog converter, which transmits at least one analog feedback signal based on the digital output signal (OUT) to the analog filter (20).

Abstract: An amplifier is described which amplifies an input signal according to a defined amplification factor, and which generates an output signal. To reduce an offset fraction of the output signal the amplifier comprises a feedback path which has lowpass characteristics and which returns the output signal in a lowpass-filtered state to an input of the amplifier. The feedback path comprises an amplifier stage as well as at least one Miller capacitance connected between an input and an output of the amplifier stage.

Abstract: The invention refers to one of a number of nodes of a communication system. The nodes are connected to a communication media for transmitting data among the nodes. Said one node comprises a communication controller, across which the node is connected to the communication media, and a bus guardian for controlling access of the communication controller to the communication media. In order to provide a cheap but nevertheless reliable way for monitoring the synchronized clock signal of a node of a communication system and in particular for detecting deviations of the synchronized clock signal it is suggested that a synchronized clock signal from the communication controller is made available to the bus guardian, and that the bus guardian comprises means for monitoring the synchronized clock signal using a bus guardian internal clock signal, which is generated by means of an electronic circuit and which is less accurate than the synchronized clock signal to be monitored.

Abstract: An integrated circuit arrangement is provided according to the present invention, including a cascoded current source (10) and an adjusting circuit (20) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source (10) by providing gate potentials (Vg1, Vg2) for current source FETs (Q1, Q2), the adjusting circuit having: a reference stage, formed by a pair of reference FETs (M2, M1), which are supplied with reference currents (Iref1, Iref2) in such a way that the current densities in the reference FETs (M2, M1) differ by a predetermined factor (N2), for providing reference gate potentials (Vgs1, Vgs2) at the gates of the reference FETs (M2, M1); a processing stage, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N2), which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), and an output FET (M9), which is connected on the source side to the adjustment potential (Vgt1&pl

Abstract: In an embodiment of the present invention, an apparatus for steering a vehicle is disclosed. The apparatus includes a back-drivable steer-by-wire system including a road wheel actuator assembly coupled to a wheel of the vehicle. The road wheel actuator assembly defines a steering axis and the steering axis is off-set from a longitudinal axis of the wheel by a positive scrub radius. In an embodiment for a method in accordance with the present invention, a method to steer a vehicle after failure of a road wheel actuator assembly in a back-drivable steer-by-wire steering system is disclosed. The method includes the acts of applying a braking force to the wheel and generating a torque on the road wheel actuator assembly by the applied braking force acting through a positive scrub radius.

Abstract: The invention relates to a method for operating a comparator (10) and a pre-amplifier (20) of an integrated circuit, which pre-amplifier is connected in series to the comparator, wherein the comparator (10) is operated with clock pulses in order to compare comparator input signals at periodical decision points (t2), wherein the pre-amplifier (20) is operated with clock pulses so as, in amplification phases (t1 to t2) which precede the decision points (t2), to amplify a signal (IN) which has been input to the pre-amplifier, and to provide the amplified signal (OUT) as a comparator input signal, and so as, in reset phases (t0 to t1) which precede the amplification phases (t1 to t2), to reset the amplification (G) to a minimum value. According to the invention, the pre-amplifier (20) is operated such that its amplification (G) during a rise phase within the amplification phase (t1 to t2) rises gradually and uniformly from the minimum value to a maximum value.

Abstract: An integrated circuit arrangement is provided according to the present invention, including a cascoded current source (10) and an adjusting circuit (20) for adjusting the operating point (Vg1, Vg2, Vx) of the cascoded current source (10) by providing gate potentials (Vg1, Vg2) for current source FETs (Q1, Q2), the adjusting circuit having: a reference stage, formed by a pair of reference FETs (M2, M1), which are supplied with reference currents (Iref1, Iref2) in such a way that the current densities in the reference FETs (M2, M1) differ by a predetermined factor (N2), for providing reference gate potentials (Vgs1, Vgs2) at the gates of the reference FETs (M2, M1); a processing stage, for providing an adjustment potential (Vgt1+V1) on the basis of the predetermined factor (N2), which is equal to the effective control voltage (Vgt1) of the first reference FET (M2) plus a predetermined additional voltage (V1), and an output FET (M9), which is connected on the source side to the adjustment potential (Vgt1&pl

Abstract: A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.

Abstract: Method for transmitting data within a communication system, the communication system comprising a communication media and a number of nodes connected to the communication media, the data being transmitted across the communication media within a communication cycle comprising a number of time slots assigned to one or more nodes of the communication system. In order to provide a possibility for a data transmission within communication cycles, which can satisfy the demands in communication systems for safety critical applications, too, it is suggested, that the communication cycle is initiated by an external event. The external event can be caused by manually setting a bit by a host, by a configurable timer in a controller host interface (CHI) or by an external trigger.

Abstract: The invention refers to a method for monitoring a communication media access schedule of a communication controller (5) of a communication system (1) by means of a bus guardian (6). The communication system (1) comprises a communication media (2) and nodes (3) connected to the communication media (2). Each node (3) comprises a communication controller (5) and a bus guardian (6) assigned to the communication controller (5). Messages are transmitted among the nodes (3) across the communication media (2) based on a cyclic time triggered communication media access scheme.