Patents by Inventor Christian Geissler

Christian Geissler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958871
    Abstract: The present invention relates to novel compounds which are particularly useful as inhibitors of bacterial glutaminyl cyclases (bacQC); pharmaceutical compositions comprising such compounds; compounds and/or pharmaceutical compositions for use in methods for treatment, in particular for use in the treatment of periodontitis and related conditions; as well as to crystals comprising bacterial glutaminyl cyclases, methods for identifying candidate compounds which may associate with the binding pocket of a bacQC and/or are bacQC inhibitors.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 16, 2024
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Christian Jäger, Linda Liebe, Daniel Ramsbeck, Miriam Linnert, Stefanie Geissler, Anke Piechotta, Diane Meitzner, Holger Cynis, Mirko Buchholz
  • Patent number: 11955462
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
  • Publication number: 20230194478
    Abstract: A radiation source device includes at least one membrane layer, a radiation source structure to emit electromagnetic or infrared radiation, a substrate and a spacer structure, wherein the substrate and the at least one membrane form a chamber, wherein a pressure in the chamber is lower than or equal to a pressure outside of the chamber, and wherein the radiation source structure is arranged between the at least one membrane layer and the substrate.
    Type: Application
    Filed: October 27, 2022
    Publication date: June 22, 2023
    Inventors: Derek Debie, Klaus Elian, Ludwig Heitzer, David Tumpold, Jens Pohl, Cyrus Ghahremani, Thorsten Meyer, Christian Geissler, Andreas Allmeier
  • Patent number: 11505450
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 22, 2022
    Assignee: Infineon Technologies AG
    Inventors: Florian Brandl, Christian Geissler, Robert Gruenberger, Claus Waechter, Bernhard Winkler
  • Patent number: 11424209
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Sven Albers, Klaus Reingruber, Georg Seidemann, Christian Geissler, Richard Patten
  • Publication number: 20220247089
    Abstract: A radio-frequency device comprises a printed circuit board and a radio-frequency package having a radio-frequency chip and a radio-frequency radiation element, the radio-frequency package being mounted on the printed circuit board. The radio-frequency device furthermore comprises a waveguide component having a waveguide, wherein the radio-frequency radiation element is configured to radiate transmission signals into the waveguide and/or to receive reception signals via the waveguide.
    Type: Application
    Filed: January 24, 2022
    Publication date: August 4, 2022
    Inventors: Walter HARTNER, Tuncay ERDOEL, Klaus ELIAN, Christian GEISSLER, Bernhard RIEDER, Rainer Markus SCHALLER, Horst THEUSS, Maciej WOJNOWSKI
  • Patent number: 11376998
    Abstract: A fastening apparatus for a child seat on a vehicle seat in a motor vehicle has a fastening element for fastening a child seat holding belt, in particular a top-tether fastening element, and a deflecting element for the child's seat holding belt. The fastening element is arranged in a region of a seating position of the vehicle seat. The fastening element is fastened in front of a front side of a backrest of the vehicle seat.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: July 5, 2022
    Assignee: Bayerische Motoren Werke Aktiengesellschaft
    Inventors: Christian Geissler, Uemit Kilincsoy
  • Publication number: 20220108976
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Application
    Filed: December 16, 2021
    Publication date: April 7, 2022
    Inventors: Georg SEIDEMANN, Klaus REINGRUBER, Christian GEISSLER, Sven ALBERS, Andreas WOLTER, Marc DITTES, Richard PATTEN
  • Patent number: 11239199
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten
  • Patent number: 11145563
    Abstract: A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Infineon Technologies AG
    Inventors: Christian Geissler, Walter Hartner, Claus Waechter, Maciej Wojnowski
  • Patent number: 10916484
    Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Robert Fehler, Francesca Arcioni, Christian Geissler, Walter Hartner, Gerhard Haubner, Thorsten Meyer, Martin Richard Niessner, Maciej Wojnowski
  • Publication number: 20210032097
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.
    Type: Application
    Filed: October 21, 2020
    Publication date: February 4, 2021
    Applicant: Infineon Technologies AG
    Inventors: Florian BRANDL, Christian GEISSLER, Robert GRUENBERGER, Claus WAECHTER, Bernhard WINKLER
  • Patent number: 10899604
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 26, 2021
    Inventors: Florian Brandl, Christian Geissler, Robert Gruenberger, Claus Waechter, Bernhard Winkler
  • Publication number: 20200384899
    Abstract: A fastening apparatus for a child seat on a vehicle seat in a motor vehicle has a fastening element for fastening a child seat holding belt, in particular a top-tether fastening element, and a deflecting element for the child's seat holding belt. The fastening element is arranged in a region of a seating position of the vehicle seat. The fastening element is fastened in front of a front side of a backrest of the vehicle seat.
    Type: Application
    Filed: October 29, 2018
    Publication date: December 10, 2020
    Inventors: Christian GEISSLER, Uemit KILINCSOY
  • Patent number: 10854590
    Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 1, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Richard Patten, Georg Seidemann, Christian Geissler
  • Patent number: 10816742
    Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
  • Publication number: 20200331748
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Applicant: Infineon Technologies AG
    Inventors: Florian BRANDL, Christian GEISSLER, Robert GRUENBERGER, Claus WAECHTER, Bernhard WINKLER
  • Patent number: 10793429
    Abstract: A production method includes providing a semiconductor substrate with a wiring layer stack having cutouts on a first main surface region of the semiconductor substrate at which MEMS components are arranged in an exposed manner in the cutouts and projecting through contact elements are arranged at metallization regions of the wiring layer stack; applying a b-stage material layer cured in an intermediate stage on the wiring layer stack, such that the cutouts are covered by the b-stage material layer and the vertically projecting through contact elements are introduced into the b-stage material layer; curing the b-stage material layer to obtain a cured b-stage material layer; thinning the cured b-stage material layer; and applying a redistribution layer (RDL) structure on the thinned, cured b-stage material layer to obtain an electrical connection between the wiring layer stack and the RDL structure via the through contact elements.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 6, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matthias Steiert, Christian Geissler, Karolina Zogal
  • Publication number: 20200273832
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Sven ALBERS, Klaus REINGRUBER, Georg SEIDEMANN, Christian GEISSLER, Richard PATTEN
  • Patent number: 10741486
    Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.
    Type: Grant
    Filed: March 6, 2016
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Klaus Reingruber, Sven Albers, Christian Geissler