Abstract: An external logic device for a network interface controller enables interrupt coalescing from a network interface controller. The network interface controller has a cause register for storing information about interrupt causes and drives an interrupt line. The external logic device is connectable to the cause register for reading the contents of the cause register, and to the interrupt line of the network interface controller and to an interrupt input of a processor for forwarding interrupts from the interrupt line of the network interface controller to the processor. The external logic device has a timer which is initializable when the interrupt line contains an interrupt, and is constructed to delay the forwarding of interrupts, depending on the current contents of the cause register, until a timeout of the timer is reached.

Abstract: A method and an apparatus for checking a main memory of a processor, which includes a cache memory and a plurality of registers. Before the memory test is carried out, a boot-up sequence which may be running at that time is interrupted, temporary data required for the memory test is written to at least one register and is held there, and the access from the cache memory to the main memory is activated. The main memory is accessed via the cache memory such that bit patterns are written to the cache memory and from there to the main memory, and are read out again from the main memory via the cache memory and are compared. The area of the main memory to be tested is larger than the size of the cache memory. The interrupted boot-up sequence is then restarted or continued after completion of the memory test.

Abstract: A method operates a processor in a real-time environment where the processor is switched from an operating state to a resting state after handling a real-time event. An auxiliary signal is generated during a near imminent occurrence of a subsequent real-time event. The processor is switched to the operating state by the signal before the subsequent real-time event occurs.

Abstract: A processor including an instruction set and registers is adapted to run a virtual machine monitor software (VMM) for hosting multiple guest operating systems, implementing an instruction translation lookaside buffer ITLB with ITLB-entries and a data translation lookaside buffer DTLB with DTLB-entries. The instruction set comprises advance instructions providing for a translation of a virtual address to a physical address based exclusively on ITLB-entries and a load instruction using the instruction translation lookaside buffer ITLB for a translation of an address of a faulting guest instruction. Furtheron, the processor includes advanced interruption control registers storing the physical address of a faulting guest instruction, an instruction bundle interruption control register storing an instruction bundle of a faulting guest instruction and/or an opcode interruption control register storing an opcode of a faulting guest instruction.

Abstract: A method for operating a virtual machine computer system running computer guest operating system processes on a central processing means in a virtualized manner includes the steps of checking the virtual TLB entry for the backing store address of the register stack engine (RSE) by the VMM and in case there is no valid TLB entry calling the guest interrupt handler, inserting valid TLB entry for the backing store address, returning to VMM, calling and proceeding with guest process.

Abstract: A method for detecting and processing sensitive non-privileged processor instructions in a virtual machine computer system running computer guest system processes in a virtualized manner on a central processing means checks the state of the virtual central processing means to be critical or not. In case the state is not critical normal virtual machine operation is continued. In case the state of the virtual central processing means is critical all instructions and thus each sensitive instruction can be emulated. To improve the performance in the critical state of the virtual CPU the instructions can be analyzed by single-stepping or pre-analyzing and setting a breakpoint before a sensitive instruction. This is followed by running the process up to the breakpoint directly and emulating the following sensitive instruction.

Abstract: The virtual machine system for running computer guest processes on a central processing means 8 virtualized by the virtual machine monitor (VMM) includes a host central processing unit 8 on which a host memory management unit 9 is implemented. The latter has a translation look-aside buffer 13 with a plurality of entries 14 each of which consists of a virtual address value 111, a physical address value 211 and a region identification value 16. The region register 17 in the host CPU 8 contains the region ID 16 of the currently running guest process. The region ID 16 is composed of a guest allocated bit field 18, in which a region sub ID is entered, and a guest system identifier bit field 19, in which an identification value uniquely identifying an associated guest system is entered.