Abstract: A sensing system includes a focal plane array, a detector dual-input circuit, a detector selector circuit and a select module. The focal plane array includes a plurality of detectors. The detector dual-input circuit combines outputs from the detectors received at a first input channel without outputs received at a second input channel. The detector selector circuit establishes a first signal path between the detectors and the first input channel and a second signal path between the detectors and the second input channel. The detector selector circuit includes a mask that maps the detectors to a first detector group or a second detector group. Based on the mask designation, the select module connects one or more of the detectors to the first signal path to establish the first detector group and connects one or more of the detectors to the second signal path to establish the second detector group.

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes an integration capacitor configured to integrate the electrical current and generate an integrator voltage. The apparatus further includes an amplifier configured to control a transistor switch coupled in series between the photodetector and the integration capacitor. The apparatus also includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Abstract: A method including collecting analog image data from an imaging array wherein the analog image data includes analog image data from a plurality of imaging pixels and from a plurality of opaque pixels. Each row of the imaging array includes both imaging pixels and opaque pixels. Opaque subtraction is performed in an analog domain, wherein biases determined in the opaque pixels for a given row of the imaging array are subtracted from the analog image data of the imaging pixels of that given row for each row of the imaging array. Performing opaque subtraction includes suppressing outliers in the analog image data from the plurality of opaque pixels. The method includes performing analog to digital conversion (ADC) on the analog image data to produce digital image data for the imaging pixels. ADC is performed after opaque subtraction in the analog domain.

Abstract: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes an integration capacitor configured to integrate the electrical current and generate an integrator voltage. The apparatus further includes an amplifier configured to control a transistor switch coupled in series between the photodetector and the integration capacitor. The apparatus also includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

Abstract: An imaging system includes a light sensor, a pulse detection imaging (PDI) circuit, and an image processing unit. The light sensor generates one or both of an image signal and a pulse signal. The pulse PDI circuit includes a first terminal in signal communication with the light sensor to receive one or both of the image signal and the pulse signal and a second terminal in signal communication with a voltage source. The image processing unit is in signal communication with the PDI circuit to receive one or both of the image signal and the pulse signal and to simultaneously perform imagery and pulse detection based on the image signal and the pulse signal, respectively.

Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

Abstract: Methods and apparatus for an imaging sensor having background subtraction including integrating photocurrent on a first capacitor, and, after a voltage on the first capacitor reaches a threshold, directing the photocurrent to a second capacitor. The first capacitor can be reset. This can be repeated a given number of times until a value on the second capacitor is read out.

Abstract: Methods and apparatus for an imaging sensor having background subtraction including integrating photocurrent on a first capacitor, and, after a voltage on the first capacitor reaches a threshold, directing the photocurrent to a second capacitor. The first capacitor can be reset. This can be repeated a given number of times until a value on the second capacitor is read out.

Abstract: A method including collecting analog image data from an imaging array wherein the analog image data includes analog image data from a plurality of imaging pixels and from a plurality of opaque pixels. Each row of the imaging array includes both imaging pixels and opaque pixels. Opaque subtraction is performed in an analog domain, wherein biases determined in the opaque pixels for a given row of the imaging array are subtracted from the analog image data of the imaging pixels of that given row for each row of the imaging array. Performing opaque subtraction includes suppressing outliers in the analog image data from the plurality of opaque pixels. The method includes performing analog to digital conversion (ADC) on the analog image data to produce digital image data for the imaging pixels. ADC is performed after opaque subtraction in the analog domain.

Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.

Abstract: A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

Abstract: An imaging system includes a light sensor, a pulse detection imaging (PDI) circuit, and an image processing unit. The light sensor generates one or both of an image signal and a pulse signal. The pulse PDI circuit includes a first terminal in signal communication with the light sensor to receive one or both of the image signal and the pulse signal and a second terminal in signal communication with a voltage source. The image processing unit is in signal communication with the PDI circuit to receive one or both of the image signal and the pulse signal and to simultaneously perform imagery and pulse detection based on the image signal and the pulse signal, respectively.

Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

Abstract: A digital pixel includes a capacitive transimpedence amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

Abstract: A buffered direct injection pixel can be operated such that it is automatically zeroed. The operation includes: during a normal operating mode, controlling a gate voltage of an injection transistor with the output of an amplifier to control a bias of photo-current source, an inverting input of the amplifier being connected to input of the injection transistor through a nulling capacitor; during a nulling operation, closing a first switch to connect the nulling capacitor directly to an output of the amplifier; during the nulling operation, closing a second switch to directly couple the input of the injection transistor to a bias voltage causing the nulling capacitor to store a difference between an output of the amplifier and the bias voltage; and after the nulling operation, providing the voltage stored on the nulling capacitor to the inverting input by opening the first and second switches.

Abstract: A pixel includes an integration capacitor coupled between a system voltage and a pump voltage source and having a first side and a second side. The pixel can be operated to have a large full well by: storing charge from a photo-current source in the integration capacitor; reading out the integration capacitor; resetting the integration capacitor by connecting the capacitor to a column line through a select transistor; while resetting, setting the pump voltage source to the system voltage; and after resetting, setting the pump voltage to ground to create a negative voltage between the integration capacitor and column line.

Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.