Abstract: The operational reliability of a heat pipe 200 provided for carrying heat dissipated by an electronic component 101 to a heat exchanger 300 is tested by using the heat pipe in the reverse direction, by providing energy in the form of heat at the exchanger 300, and by measuring the propagation time ?P of the heat from the exchanger to the electronic component. Application to heat pipe tests in onboard computers.

Abstract: The present invention relates to an alarm management system intended to be carried onboard an aircraft. More precisely, the invention is aimed at improving the certainty level relating to the integrity of the announcements of faults or information intended for the pilot and based on voice syntheses. For this purpose, the present invention proposes a device and a method for detecting the digital origin of an analog signal providing a validity signal (VAL) enabling the voice announcements made to the pilot to be rendered secure.

Abstract: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10?9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Abstract: The present invention relates to an alarm management system intended to be carried onboard an aircraft. More precisely, the invention is aimed at improving the certainty level relating to the integrity of the announcements of faults or information intended for the pilot and based on voice syntheses. For this purpose, the present invention proposes a device and a method for detecting the digital origin of an analog signal providing a validity signal (VAL) enabling the voice announcements made to the pilot to be rendered secure.

Abstract: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10?9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Abstract: The operational reliability of a heat pipe 200 provided for carrying heat dissipated by an electronic component 101 to a heat exchanger 300 is tested by using the heat pipe in the reverse direction, by providing energy in the form of heat at the exchanger 300, and by measuring the propagation time ?P of the heat from the exchanger to the electronic component. Application to heat pipe tests in onboard computers.

Abstract: This switch comprises a central buffer memory (30) for temporarily storing the data traffic which it receives, the time for performing the routings and for carrying out the resendings of the messages that it receives. It is noteworthy in that its central buffer memory (30) and the accesses to this buffer memory (30) by its various input/output ports are managed by a sequencer (40) in such a way as to have an implicit measure of the timescale for storing the messages in the central buffer memory (30) and to minimize the number of switchings which generate consumption and electromagnetic disturbances. Advantageously, the buffer memory is embodied with the aid of several modules (A, B, C, D) operating in parallel.

Abstract: This method enables the reconstitution of messages fragmented in packets. It comprises a process for taking a census of the packets made available to a terminal (1) by transmission networks (Na, Nb) and a process for the reassembling of messages from packets listed by the census-taking process. These two processes implement a table of pointers pointing at the packets made available to the terminal (1) by the transmission networks (Na, Nb), sorted out by membership message, said pointers being placed, for each membership message, in a stack according to the order in which the packets that they point at are made available to the terminal (1) and being provided with information or status fields enabling the reporting of doubles or discrepancies between the order in which the packets of a stack are made available and the natural order of the message fragments constituted by the payloads of the packets, and the fate of the packet pointed at during the reassembling process.

Abstract: The invention relates to the selection and sorting, by a device having access to one or more packet transmission networks, of the packets relating to it, from among the entirety of the packets made available by the networks, given that the packets respect at least two layers of protocols or even more.

Abstract: This method consists in making a routing automaton carry out verifications on the integrity of the packets arriving at the packet switch, their periods of stay in the packet switch, their matching with the virtual paths that they claim to take as well as the routings proper, within the packet switch, of the datagrams that have satisfactorily undergone the verification. The routing automaton is provided with a random access memory of instructed values containing a table of virtual path local descriptors. The processing time of the automaton is divided into a repetitive sequence of time slots individually allocated to the different input ports of the packet switch.

Abstract: The systematic, and possibly repeated, acquisition of several distinct quantities for exploitation by a user system by utilizing a multiplexer with staged architecture without all inputs hard-wired. Each multiplexer stage is addressed by an elementary counter chained with elementary counters for addressing lower stages. The multiplexer inputs are scanned by regularly incrementing the chain of counters. If no precaution is taken, all the multiplexer inputs are scanned without considering their possible absences. To remedy this drawback a first elementary counter addresses the first stage of adjustable counting capacity switches, the elementary counters can address intermediate stages of the switches with controllable shunting circuits, and a global counter is reconfigured, at the end of each counting cycle of the first elementary counter, by commands adjusting the first elementary counter capacity, and activating or inhibiting the shunting circuits.

Abstract: The invention relates to the selection and sorting, by an installation having access to one or more packet transmission networks, of the packets relating to it, from among the entirety of the packets made available by the networks, given that the packets respect at least two layers of protocols or even more.

Abstract: This switch comprises a central buffer memory (30) for temporarily storing the data traffic which it receives, the time for performing the routings and for carrying out the resendings of the messages that it receives. It is noteworthy in that its central buffer memory (30) and the accesses to this buffer memory (30) by its various input/output ports are managed by a sequencer (40) in such a way as to have an implicit measure of the timescale for storing the messages in the central buffer memory (30) and to minimize the number of switchings which generate consumption and electromagnetic disturbances. Advantageously, the buffer memory is embodied with the aid of several modules (A, B, C, D) operating in parallel.

Abstract: This method enables the reconstitution of messages fragmented in packets. It comprises a process for taking a census of the packets made available to a terminal (1) by transmission networks (Na, Nb) and a process for the reassembling of messages from packets listed by the census-taking process. These two processes implement a table of pointers pointing at the packets made available to the terminal (1) by the transmission networks (Na, Nb), sorted out by membership message, said pointers being placed, for each membership message, in a stack according to the order in which the packets that they point at are made available to the terminal (1) and being provided with information or status fields enabling the reporting of doubles or discrepancies between the order in which the packets of a stack are made available and the natural order of the message fragments constituted by the payloads of the packets, and the fate of the packet pointed at during the reassembling process.

Abstract: An input/output controller interacts with a central processing unit of a computer which communicates with peripheral electronic equipment. The link with the central processor unit is produced with an input serial line and at least one output serial line. It receives instructions of a first type from the central processing unit and instructions of at least a second kind which are stored in the memory external to the central processing unit. These are processed using a sequencer device which allocates time slots to the instructions according to their type. This device is especially useful in the field of avionics and flight management systems.

Abstract: This method consists in making a routing automaton (50) carry out verifications on the integrity of the packets arriving at the packet switch (1), their periods of stay in the packet switch (1), their matching with the virtual paths that they claim to take as well as the routings proper, within the packet switch (1), of the datagrams that have satisfactorily undergone the verification. The routing automaton (50) is provided with a random access memory of instructed values (60) containing a table of virtual path local descriptors. The processing time of the automaton is divided into a repetitive sequence of time slots individually allocated to the different input ports (21, 22, 23) of the packet switch (1).

Abstract: A method for the reception and preprocessing of digital messages, with a view to their use by a handling processor. The method associates a tag identifying each message capable of being received with a descriptor of preprocessing operations to be applied to the message. The tag of certain messages is associated with a sequence of descriptors of instructions capable of being run. The descriptor is stored in a memory at an address calculated with the aid of the tag of the associated message. Upon reception of a message, the tag of the received message is read, the address of the descriptor is determined with the aid of the tag, the descriptor is read at the address thus calculated, and the instruction sequence associated with the tag of the message is run if the descriptor is of the instruction type.

Abstract: The present invention concerns an input/output controller intended to interact with a central processor unit (UC) of a computer which communicates with peripheral electronic equipment (EQ). It is connected on the one hand to the central processor unit (UC) and on the other hand to the peripheral electronic equipment (EQ). The link with the central processor unit (UC) is produced with an input serial line (Ise) and at least one output serial line (Iss1, Iss2). It receives instructions of a first type (CO4) from the central processor unit (UC) and instructions of at least one second type (CO1, CO2, CO3) which are stored in a memory (PROM) external to the central processor unit which it processes using a sequencer device (SEQ) which allocates time slots to the instructions according to their type.

Abstract: The disclosure relates to the acquisition of a binary analog signal at input of a digital integrated circuit after its range of voltage variation has been matched with that acceptable by the digital integrated circuit by means of a resistive divider bridge. It is usual to define the architecture of an ASIC digital integrated circuit on the basis of libraries of pre-characterized cells. The disclosed device is designed to increase the possibilities of choice open to the integrated circuit designer, in enabling him to one pre-characterized cell of a Schmitt trigger for its top switching threshold and another for its bottom switching threshold. It consists of a circuit comprising, at input, a bank of Schmitt triggers of different types, followed by a discrete-rendering logic circuit deducing the logic state of the binary input analog signal of the combination of the output states of the input Schmitt triggers.

Abstract: Phase-locked loop oscillators that are designed to set the clock rate of electronic circuits based on combinations of logic circuits and to be integrated, at the same time as these electronic circuits, into one and the same chip. There is proposed a phase-locked loop oscillator based purely on combinations of logic circuits so as not to make use of integration techniques different from those used for the electronic circuits based on combinations of logic circuits, for which they are designed to set the clock rate.