Abstract: A circuit for biasing a field effect transistor using two voltages. With said circuit, the bias point of the transistor may be varied by varying the source bias voltage. At least one access electrode is polarized from a bias voltage through a first secondary transistor operating as saturable load. The gate of the main transistor and the gate of the saturable load are connected at two points of a divider bridge, supplied by the two bias voltages and comprising at least two resistors and a second secondary transistor. The gate-source voltage of said saturable load follows the gate-source voltage of said main transistor.

Abstract: A vertical channel field effect transistor is disclosed which has a specialized grid structure in order to improve the characteristics. The improved field effect transistor utilizes an arrangement of two sets of parallel teeth which intersect to form a mesh-like structure in order to produce conduction filaments. The device is particularly applicable to field effect transistor structures which have two-grid transistors.