Patents by Inventor Christian Zistl
Christian Zistl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8698312Abstract: The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.Type: GrantFiled: January 31, 2005Date of Patent: April 15, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: James Werking, Frank Feustel, Christian Zistl, Peter Huebler
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Patent number: 7737021Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.Type: GrantFiled: September 30, 2002Date of Patent: June 15, 2010Assignee: Globalfoundries Inc.Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas John Kepler
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Patent number: 7416992Abstract: By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.Type: GrantFiled: November 28, 2005Date of Patent: August 26, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Matthias Lehr, Peter Huebler, Christian Zistl
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Publication number: 20060246711Abstract: By using a non-metallic hard mask for patterning low-k dielectric materials of advanced semiconductor devices, an enhanced degree of etch fidelity is obtained. The present invention may readily be applied to via first-trench last, trench first-via last schemes.Type: ApplicationFiled: November 28, 2005Publication date: November 2, 2006Inventors: Matthias Lehr, Peter Huebler, Christian Zistl
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Patent number: 7005380Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.Type: GrantFiled: May 28, 2003Date of Patent: February 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Massud Aminpur, Gert Burbach, Christian Zistl
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Publication number: 20050242435Abstract: The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides an increased overall mechanical stability, especially during the packaging of the device. Consequently, cracking and delamination, as frequently observed in high end low-k interconnect structures, may significantly be reduced, even if organic package substrates are used.Type: ApplicationFiled: January 31, 2005Publication date: November 3, 2005Inventors: James Werking, Frank Feustel, Christian Zistl, Peter Huebler
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Patent number: 6881665Abstract: A method is provided, the method comprising forming a dielectric layer above a structure layer, forming a hard mask layer above the dielectric layer, and forming at least one trench opening and at least one upper portion of a first via opening in the dielectric layer through the hard mask layer. The method also comprises forming a low viscosity photoresist layer above the at least one trench opening and the at least one upper portion of the first via opening in the dielectric layer.Type: GrantFiled: August 9, 2000Date of Patent: April 19, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Ting Yiu Tsui, Stephen Keetai Park, Christian Zistl
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Patent number: 6806191Abstract: A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.Type: GrantFiled: November 26, 2002Date of Patent: October 19, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Christian Zistl, Jörg Hohage, Hartmut Rülke, Peter Hübler
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Publication number: 20040121599Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.Type: ApplicationFiled: May 28, 2003Publication date: June 24, 2004Inventors: Massud Aminpur, Gert Burbach, Christian Zistl
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Publication number: 20030232466Abstract: An SOI substrate includes a diffusion barrier layer, the layer thickness and composition of which is selected so as to substantially prevent copper atoms and ions from diffusing through the diffusion barrier layer. The diffusion barrier layer is located to substantially reduce the deleterious effect of copper that may be introduced into a semiconductor device from the back side of the substrate during various manufacturing stages of the semiconductor device. In one particular example, a silicon wafer with a silicon nitride layer as a diffusion barrier layer and a silicon wafer with an oxide layer is bonded. After separation, an SOI substrate is obtained that has superior characteristics with respect to resistance against copper back side diffusion.Type: ApplicationFiled: November 27, 2002Publication date: December 18, 2003Inventors: Christian Zistl, Johannes Groschopf, Massud Aminpur
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Publication number: 20030224599Abstract: A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.Type: ApplicationFiled: November 26, 2002Publication date: December 4, 2003Inventors: Christian Zistl, Jorg Hohage, Hartmut Rulke, Peter Hubler
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Patent number: 6610594Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.Type: GrantFiled: July 10, 2001Date of Patent: August 26, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Paul R. Besser, Fred Cheung
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Patent number: 6514844Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.Type: GrantFiled: April 23, 2001Date of Patent: February 4, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jeremy I. Martin, Eric M. Apelgren, Christian Zistl, Paul R. Besser, Srikantewara Dakshina-Murthy, Jonathan B. Smith, Nick Kepler, Fred Cheung
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Publication number: 20030013296Abstract: A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.Type: ApplicationFiled: July 10, 2001Publication date: January 16, 2003Inventors: Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Paul R. Besser, Fred Cheung
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Patent number: 6500755Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.Type: GrantFiled: December 6, 2000Date of Patent: December 31, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas John Kepler
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Patent number: 6406993Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.Type: GrantFiled: March 10, 2000Date of Patent: June 18, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas J. Kepler
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Publication number: 20020068436Abstract: The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.Type: ApplicationFiled: December 6, 2000Publication date: June 6, 2002Inventors: Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B Smith, Eric M. Apelgren, Christian Zistl, Jeremy I. Martin, Lie Larry Zhao, Nicholas John Kepler
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Patent number: 6313538Abstract: A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.Type: GrantFiled: January 21, 2000Date of Patent: November 6, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Christian Zistl, Paul R. Besser, Eric M. Apelgren, Nicholas J. Kepler, Srikanteswara Dakshina-Murthy
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Patent number: 6268255Abstract: The present invention is directed to a method of making a semiconductor device. In one illustrative embodiment, the method comprises forming a first layer comprised of polysilicon, forming a second layer comprised of a refractory metal above the layer of polysilicon and converting at least a portion of the second layer to a first metal silicide. The method further comprises forming an anti-reflective coating layer above the layer of refractory metal or the first metal silicide layer, and patterning the first metal silicide layer and the layer of polysilicon to define a gate stack comprised of a first metal silicide region and a layer of polysilicon, forming a plurality of source/drain regions in the substrate, forming a third layer comprised of a refractory metal above at least the gate stack and the source/drain regions, and converting at least a portion of the third layer to a second metal silicide region.Type: GrantFiled: January 6, 2000Date of Patent: July 31, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Paul R. Besser, Christian Zistl, Nicholas J. Kepler
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Patent number: 6261963Abstract: A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure.Type: GrantFiled: July 7, 2000Date of Patent: July 17, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Larry Zhao, Paul R. Besser, Eric M. Apelgren, Christian Zistl, Jonathan B. Smith