Patents by Inventor Christina M. Boyko
Christina M. Boyko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6931726Abstract: A method of making an interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the method includes the steps of providing a substrate having at least one plated through hole therein, and positioning a first conductive layer and a second conductive layer over the at least one plated through hole on opposing surfaces of the substrate. The method includes positioning a layer of dielectric material thereon on the first conductive layer. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, and at least a pair of conductive layers that can carry signals, and power.Type: GrantFiled: May 13, 2003Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Donald S. Farquhar, Konstantinos I. Papathomas
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Patent number: 6775907Abstract: The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. Steps required to achieve this objective include adhering an electroless plated copper commoning layer to a surface roughened dielectric substrate. Subsequently, the commoning layer is photolithographically personalized by covering the commoning layer with a resist and then uncovering predetermined areas of the aforementioned commoning layer. Consequently, the semi-additive method involves electroplating copper onto the uncovered areas of the commoning layer, thereby generating copper features and circuitry. Finally, the semi-additive process requires the stripping of the remaining photoresist, and the unplated electroless copper layer is etched in order to electronically isolate the copper features and circuitry lines.Type: GrantFiled: September 14, 2000Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Robert J. Day, Kristen A. Stauffer
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Patent number: 6776852Abstract: A process of removing excess holefill material from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.Type: GrantFiled: January 14, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Brian E. Curcio, Donald S. Farquhar, Michael Wozniak
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Patent number: 6660945Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.Type: GrantFiled: October 16, 2001Date of Patent: December 9, 2003Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Donald S. Farquhar, Konstantinos I. Papathomas
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Publication number: 20030172525Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.Type: ApplicationFiled: May 12, 2003Publication date: September 18, 2003Applicant: International Business Machines CorporationInventors: Christina M. Boyko, Donald S. Farquhar, Konstantinos I. Papathomas
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Publication number: 20030131870Abstract: A process of removing holefill residue from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.Type: ApplicationFiled: January 14, 2002Publication date: July 17, 2003Inventors: Christina M. Boyko, Brian E. Curcio, Donald S. Farquhar, Michael Wozniak
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Publication number: 20030070839Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.Type: ApplicationFiled: October 16, 2001Publication date: April 17, 2003Inventors: Christina M. Boyko, Donald S. Farquhar, Konstantinos I. Papathomas
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Patent number: 6212769Abstract: The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. A roughened copper foil is laminated to a dielectric substrate. The foil is subsequently removed from the dielectric to create a roughened, irregular surface on the dielectric substrate. Vertical angle through holes and blind holes are formed in the substrate. A uniform copper commoning layer is electrolessly plated to the roughened dielectric substrate and through holes. A photoresist is applied on the surface of the electroless plated layer and irradiated through a mask having printed circuit features. After developing the photoresist the uncovered electroless layer is electrolytically plated to create the final features and circuitry. After stripping the remaining photoresist the unplated electroless copper layer is etched to electronically isolate the copper features and circuitry lines.Type: GrantFiled: June 29, 1999Date of Patent: April 10, 2001Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Robert J. Day, Kristen A. Stauffer
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Patent number: 6121069Abstract: A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.Type: GrantFiled: September 3, 1999Date of Patent: September 19, 2000Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Anthony P. Ingraham, Voya R. Markovich, David J. Russell
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Patent number: 5953623Abstract: A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.Type: GrantFiled: April 10, 1997Date of Patent: September 14, 1999Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Anthony P. Ingraham, Voya R. Markovich, David J. Russell
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Patent number: 5571593Abstract: The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.Type: GrantFiled: June 6, 1995Date of Patent: November 5, 1996Assignee: International Business Machines CorporationInventors: Roy L. Arldt, Christina M. Boyko, Burtran J. Cayson, Richard M. Kozlowski, Joseph D. Kulesza, John M. Lauffer, Philip C. Liu, Voya R. Markovich, Issa S. Mahmoud, James F. Muska, Kostas Papathomas, Joseph G. Sabia, Richard A. Schumacher
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Patent number: 5472735Abstract: The present invention relates to a method for selectively electroetching a metal from an electrical device having the steps of: immersing the electrical device in an etching solution; immersing a cathode in the etching solution; applying an etching potential to a preselected area of the metal; and maintaining a passivation potential at the metal to remain unetched. The metal to remain unetched is not electrically connected to the preselected area and the passivation potential does not equal the etching potential.The present invention further relates to a method of forming an electrical connection to the inner layers of a multilayer circuit board having a copper foil surface layer and copper containing inner layers.Type: GrantFiled: December 8, 1994Date of Patent: December 5, 1995Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Richard W. Carpenter, Raymond T. Galasco, Krystyna W. Semkow, Herbert Wegener
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Patent number: 5450290Abstract: The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon.Type: GrantFiled: February 14, 1994Date of Patent: September 12, 1995Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Francis J. Bucek, Richard W. Carpenter, Voya R. Markovich, Darleen Mayo, Cindy M. Reidsema, Joseph G. Sabia
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Patent number: 5374338Abstract: The present invention relates to a method for selectively electroetching a metal from an electrical device having the steps of: immersing the electrical device in an etching solution; immersing a cathode in the etching solution; applying an etching potential to a preselected area of the metal; and maintaining a passivation potential at the metal to remain unetched. The metal to remain unetched is not electrically connected to the preselected area and the passivation potential does not equal the etching potential.The present invention further relates to a method of forming an electrical connection to the inner layers of a multilayer circuit board having a copper foil surface layer and copper containing inner layers.Type: GrantFiled: October 27, 1993Date of Patent: December 20, 1994Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Richard W. Carpenter, Raymond T. Galasco, Krystyna W. Semkow, Herbert Wegener
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Patent number: 4960634Abstract: A composition of enhanced thermal conductivity which comprises a tetrabrominated diglycidyl ether polyepoxide; and epoxy polymer having an epoxy functionality of 3.5 to 6; zinc oxide and curing agents; and use thereof.Type: GrantFiled: March 14, 1990Date of Patent: October 2, 1990Assignee: International Business Machines CorporationInventors: Christina M. Boyko, Craig N. Johnston, James R. Loomis, Carl E. Samuelson, Ricahrd A. Schumacher