Patents by Inventor Christine Sung-An Hau-Riege
Christine Sung-An Hau-Riege has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11508725Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.Type: GrantFiled: January 30, 2020Date of Patent: November 22, 2022Assignee: QUALCOMM INCORPORATEDInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Publication number: 20200168604Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.Type: ApplicationFiled: January 30, 2020Publication date: May 28, 2020Inventors: Seid Hadi RASOULI, Michael Joseph BRUNOLLI, Christine Sung-An HAU-RIEGE, Mickael MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON
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Patent number: 10600785Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.Type: GrantFiled: March 21, 2018Date of Patent: March 24, 2020Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Patent number: 9972624Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.Type: GrantFiled: August 23, 2013Date of Patent: May 15, 2018Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
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Patent number: 9941156Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.Type: GrantFiled: April 1, 2015Date of Patent: April 10, 2018Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Vidhya Ramachandran, Christine Sung-An Hau-Riege, John Jianhong Zhu, Jeffrey Junhao Xu, Jihong Choi, Jun Chen, Choh Fei Yeap
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Publication number: 20160293475Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.Type: ApplicationFiled: April 1, 2015Publication date: October 6, 2016Inventors: Shiqun Gu, Vidhya Ramachandran, Christine Sung-An Hau-Riege, John Jianhong Zhu, Jeffrey Junhao Xu, Jihong Choi, Jun Chen, Choh Fei Yeap
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Patent number: 9171782Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.Type: GrantFiled: August 6, 2013Date of Patent: October 27, 2015Assignee: QUALCOMM IncorporatedInventors: Christine Sung-An Hau-Riege, You-Wen Yau, Kevin Patrick Caffey, Lizabeth Ann Keser, Gene Hyde McAllister, Reynante Tamunan Alvarado, Steve Joseph Bezuk, Damion Bryan Gastelum
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Publication number: 20150054568Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: QUALCOMM INCORPORATEDInventors: Seid Hadi RASOULI, Michael Joseph BRUNOLLI, Christine Sung-An HAU-RIEGE, Mickael MALABRY, Sucheta Kumar HARISH, Prathiba BALASUBRAMANIAN, Kamesh MEDISETTI, Nikolay BOMSHTEIN, Animesh DATTA, Ohsang KWON
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Publication number: 20150041982Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: QUALCOMM IncorporatedInventors: Christine Sung-An Hau-Riege, You-Wen Yau, Kevin Patrick Caffey, Lizabeth Ann Keser, Gene H. McAllister, Reynante Tamunan Alvarado, Steve J. Bezuk, Damion Bryan Gastelum