Abstract: The invention relates to a biosensor that is provided with a first electrode having a first holding area and a second electrode having a second holding area for holding probe molecules which can bind macromolecular biopolymers to be detected. The first electrode and the second electrode are arranged in relation to one another in such a way that essentially unbent field lines of a generated electric field can be embodied between said electrodes.

Abstract: A method for fabricating a microelectronic circuit having an improved electrically conductive element. The method includes providing a finished processed microelectronic circuit having a monolithically integrated coil and having a passivation layer situated above at least the monolithically integrated coil. The method further comprises removing at least part of the passivation layer above the monolithically integrated coil and applying a metal layer above the monolithically integrated coil so that the metal layer is electrically coupled to the monolithically integrated coil.

Abstract: The invention relates to a bag comprising at least one integrated communication interface, which is used to electrically interconnect a plurality of electric devices contained in said bag, in such a way that data can be transferred between the electric devices.

Abstract: The device for voltage multiplication on the basis of a boosted charge pump is used, for example, as on-chip high-voltage generator in EEPROMs and flash EEPROMs. As a result of charging the pump capacitances via tristate drivers and a simplified timing scheme, the power loss is reduced and chip area is saved.

Abstract: A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Abstract: An apparatus for voltage multiplication of the kind required, for example, for programming flash EEPROMs. The apparatus has the advantage that comparatively simple and good regulation of the output voltage can be produced even in integrated circuits in which severe fluctuations in the supply voltage may be allowed.

Abstract: A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Abstract: A circuit configuration for producing negative voltages includes a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection. A second transistor has a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor. A second capacitor has a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection. The transistors are MOS transistors produced in a triple well.

Abstract: A photodiode-FET combination having an optimized layer structure wherein the photodiode and the FET are separated from one another by a separating trench and are separated from the substrate by barrier layers forming a pn-junction in order to avoid tributary currents. A layer sequence is provided formed of an absorption layer grown on in surface-wide fashion, of a photodiode layer that is likewise grown on in surface-wide fashion and which is etched back to the region of light incidence in the region of the photodiode, of a channel layer in the region of the FET, and of a cover layer on the channel layer which forms a gate.

Abstract: A PIN-FET combination having a basic layer, a first semiconductor layer as an absorption layer or, resepectively, a buffer layer, a second semiconductor layer as a contact layer or, respectively, as a channel layer and a third semiconductor layer as a cover layer grown surface-wide on a substrate. The p.sup.+ -region of the photodiode and, respectively, the gate region of the FET being fashioned therein. The basic layer is undoped or n-doped in the region of the photodiode and is p-doped in the region of the FET and a surface-wide, p-doped layer portion is present in the region of the FET between the channel layer and the substrate.

Abstract: A contact structure on indium-containing III-V semiconductor material is comprised of a four layer sequence consisting of an indium layer in direct contact with the semiconductor material, a zinc layer in contact with the indium layer, a chromium-nickel or chromium or palladium or platinum layer in contact with the zinc layer and a gold layer for external contacting with a lead. An exemplary embodiment of such contact structure exhibits specific contact resistance ranging between about 10.sup.-4 and 10.sup.-5 ohm.multidot. cm.sup.2.