Patents by Inventor Christoph Raisch

Christoph Raisch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200264912
    Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
  • Publication number: 20200264995
    Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Sascha Junghans, Peter Dana Driever
  • Publication number: 20200264917
    Abstract: An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory operationally connected with the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Inventors: Marco Kraemer, Christoph Raisch, Donald William Schmidt, Bernd Nerz, Frank Siegfried Lehnert, Peter Dana Driever
  • Publication number: 20200264994
    Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory section assigned to a second guest operating system hosting the first operating system and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Donald William Schmidt, Bernd Nerz, Peter Dana Driever
  • Publication number: 20200264911
    Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. In addition, the bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 20, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Bernd Nerz, Donald William Schmidt, Peter Dana Driever
  • Publication number: 20200250112
    Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.
    Type: Application
    Filed: January 29, 2020
    Publication date: August 6, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever
  • Publication number: 20200252304
    Abstract: Embodiments for managing bare metal networking in a cloud computing environment. A network communication module that receives a configuration instruction over a direct network link from an external remote management device on a network endpoint may be initialized.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hubertus FRANKE, Christoph RAISCH, Marcio Augusto SILVA, Gheorghe ALMASI, Marc COCHRAN, Alan ROSS
  • Publication number: 20200249943
    Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.
    Type: Application
    Filed: January 29, 2020
    Publication date: August 6, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever
  • Publication number: 20200249944
    Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.
    Type: Application
    Filed: January 29, 2020
    Publication date: August 6, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever
  • Publication number: 20200250115
    Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.
    Type: Application
    Filed: January 29, 2020
    Publication date: August 6, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Peter Dana Driever, Brenton Belmar
  • Publication number: 20200193039
    Abstract: A cloud computing system includes a virtual server outputs non-encrypted data and receives encrypted data in response to receiving a write request signal and a read request signal. A hosting server hypervisor receives the write request signal and the read request signal. In response to receiving the write request signal the hosting server hypervisor writes encrypted data corresponding to the write request signal into a storage device. In response to receiving the read request signal the hosting server hypervisor obtains encrypted data corresponding to a data read request signal from the storage device and outputs the encrypted data. A secure channel sub-system is installed between the at least one virtual server and the hosting server hypervisor.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Christoph Vincent Schlameuss, Christoph Raisch, Carsten Otte, Marco Kraemer, Jakob Christopher Lang, Stefan Roscher
  • Publication number: 20200117474
    Abstract: A method, computer program product, and system includes a processor(s) connecting a first computer system to a boot swarm, initiating formation of a peer to peer network. The processor(s) receive a request from a second computer system, a request for a file. The processor(s) configure the second computer system, including implementing a client application hosted from a resource in the first computer system, to facilitate the second computer system joining the peer to peer network. The processor(s) determine immediate peer(s) in the peer to peer network available to provide the file to the second computer system. The processor(s) generate a magnet link that includes a listing of address(es) of the immediate peer(s), ranking address(es) from best source to worst source for downloading the file. The processor(s) provide the second computer system with the magnet link to utilize in downloading the file from a peer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Alol A. Crasta, Harshal S. Patil, Kishorekumar G. Pillai, Christoph Raisch, Nishant Ranjan
  • Patent number: 10606759
    Abstract: A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marco Kraemer, Carsten Otte, Christoph Raisch
  • Publication number: 20200097322
    Abstract: Embodiments of the present invention disclose a method, computer program product, and system for processing a thread of execution on a plurality of independent processing cores. In various embodiments, a run state and a local maximum thermal power is assigned to each of at least part of the cores. A first one of the cores is set to the active state. The thread on the first core in the active state is processed. The processing of the thread on the first core for fulfilment of an interrupt condition is monitored. A second one of the cores is set to the active state. The processing of the thread on the first core is halted. The processing of the thread to the second core is transferred. The processing of the thread on the second core in the active state continues and the first core is set to the cooling state.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventors: Marco Kraemer, Matteo Michel, Carsten Otte, Christoph Raisch
  • Patent number: 10579395
    Abstract: A method, computer program product, and system includes a processor(s) connecting a first computer system to a boot swarm, initiating formation of a peer to peer network. The processor(s) receive a request from a second computer system, a request for a file. The processor(s) configure the second computer system, including implementing a client application hosted from a resource in the first computer system, to facilitate the second computer system joining the peer to peer network. The processor(s) determine immediate peer(s) in the peer to peer network available to provide the file to the second computer system. The processor(s) generate a magnet link that includes a listing of address(es) of the immediate peer(s), ranking address(es) from best source to worst source for downloading the file. The processor(s) provide the second computer system with the magnet link to utilize in downloading the file from a peer.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alol A. Crasta, Harshal S. Patil, Kishorekumar G. Pillai, Christoph Raisch, Nishant Ranjan
  • Publication number: 20200065009
    Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: MARCO KRAEMER, CARSTEN OTTE, CHRISTOPH RAISCH
  • Patent number: 10572268
    Abstract: A method, computer program product, and system includes a processor(s) connecting a first computer system to a boot swarm, initiating formation of a peer to peer network. The processor(s) receive a request from a second computer system, a request for a file. The processor(s) configure the second computer system, including implementing a client application hosted from a resource in the first computer system, to facilitate the second computer system joining the peer to peer network. The processor(s) determine immediate peer(s) in the peer to peer network available to provide the file to the second computer system. The processor(s) generate a magnet link that includes a listing of address(es) of the immediate peer(s), ranking address(es) from best source to worst source for downloading the file. The processor(s) provide the second computer system with the magnet link to utilize in downloading the file from a peer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alol A. Crasta, Harshal S. Patil, Kishorekumar G. Pillai, Christoph Raisch, Nishant Ranjan
  • Patent number: 10545683
    Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marco Kraemer, Carsten Otte, Christoph Raisch
  • Patent number: 10545681
    Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marco Kraemer, Carsten Otte, Christoph Raisch
  • Publication number: 20190394138
    Abstract: Aspects of the invention include receiving an input/output (I/O) request that includes a data stream from a host processor. The receiving is at a network adapter of a storage controller that manages storage for the host processor. The storage controller includes a storage buffer to store data received from the host processor before migrating it to the storage. The storage controller also includes a data cache. It is determined whether the storage buffer has enough free space to store the received data stream. Based at least in part on determining that the storage buffer has enough free space to store the received data stream, the received data stream is stored by the network adapter in the storage. Based at least in part on determining that the storage buffer does not have enough free space to store the received data stream, the received data stream is stored in the data cache.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Christoph Raisch, Kishorekumar G. Pillai, Alol Antony Crasta, Raghavan Devanathan