Patents by Inventor Christophe Goncalves

Christophe Goncalves has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device for controlling the activity of modules of an array of memory modules
    Patent number: 8036012
    Abstract: A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: October 11, 2011
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Claire-Marie Lachaud, Christophe Goncalves
  • DEVICE FOR CONTROLLING THE ACTIVITY OF MODULES OF AN ARRAY OF MEMORY MODULES
    Publication number: 20100124100
    Abstract: A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 20, 2010
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Claire-Marie Lachaud, Christophe Goncalves
  • Voltage level translator
    Patent number: 7449933
    Abstract: A low to high voltage level converter includes first and second n-channel transistors arranged to force to the ground voltage a first connection node and a second connection node, respectively. A boosting circuit operates to boost an input voltage of at least one of a first and second control nodes for the first and second n-channel transistors above a low voltage level. The converter further includes first and second cross-coupled p-channel transistors arranged to force to the high voltage level the first connection node and the second connection node, respectively. A digital output signal is taken from one of the first and second connection nodes.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: November 11, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Christophe Goncalves, Bruno Salvador, Olivier Goducheau
  • Voltage level translator
    Publication number: 20070139092
    Abstract: A low to high voltage level converter includes first and second n-channel transistors arranged to force to the ground voltage a first connection node and a second connection node, respectively. A boosting circuit operates to boost an input voltage of at least one of a first and second control nodes for the first and second n-channel transistors above a low voltage level. The converter further includes first and second cross-coupled p-channel transistors arranged to force to the high voltage level the first connection node and the second connection node, respectively. A digital output signal is taken from one of the first and second connection nodes.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Christophe Goncalves, Bruno Salvador, Olivier Goducheau