Abstract: An optoelectronic device includes a carrier substrate and a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and including alternating first layers. A set of epitaxial layers disposed over the lower DBR includes a quantum well structure. An upper DBR stack disposed over the set of epitaxial layers includes alternating second layers. Electrodes apply an excitation current to the quantum well structure. At least one of the electrodes includes a metal ring disposed at an inner side of at least one of the DBR stacks in proximity to the quantum well structure. One or more metal vias pass through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks.

Abstract: An integrated emitter device incudes a silicon die, including an array of control circuits, and a plurality of integrated emitter modules disposed on the silicon die. Each integrated emitter module includes a single epitaxial stack comprising multiple layers of III-V semiconductor compounds, which define a vertical emitter including an optically active layer and upper and lower distributed Bragg reflectors (DBRs) on opposing sides of the optically active layer, and a transistor in series with the vertical emitter and including a terminal in contact with a respective one of the control circuits, so as to actuate the vertical emitter in response to a control signal applied to the terminal by the respective one of the control circuits.

Abstract: A multispectral sensing device includes a first die, including silicon, which is patterned to define a first array of sensor elements, which output first electrical signals in response to optical radiation that is incident on the device in a band of wavelengths less than 1000 nm that is incident on the front side of the first die. A second die has its first side bonded to the back side of the first die and includes a photosensitive material and is patterned to define a second array of sensor elements, which output second electrical signals in response to the optical radiation that is incident on the device in a second band of wavelengths greater than 1000 nm that passes through the first die and is incident on the first side of the second die. Readout circuitry reads the first electrical signals and the second electrical signals serially out of the device.

Abstract: An optoelectronic device includes a base chip, including a silicon die having a photodiode disposed at its front surface and a first anode contact and a first cathode contact disposed on the front surface. A laser diode driver circuit on the silicon die supplies an electrical drive signal between the first anode contact and the first cathode contact. An emitter chip includes a III-V semiconductor die, which is mounted with its front side facing toward the front surface of the silicon die. A second anode contact and a second cathode contact are disposed on the front side of the III-V semiconductor die in electrical communication with the first anode contact and the first cathode contact. A VCSEL is disposed on the front side of the III-V semiconductor die in coaxial alignment with the photodiode and receives the drive signal from the second anode contact and the second cathode contact.

Abstract: An optoelectronic device includes a carrier substrate and a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and including alternating first layers. A set of epitaxial layers disposed over the lower DBR includes a quantum well structure. An upper DBR stack disposed over the set of epitaxial layers includes alternating second layers. Electrodes apply an excitation current to the quantum well structure. At least one of the electrodes includes a metal ring disposed at an inner side of at least one of the DBR stacks in proximity to the quantum well structure. One or more metal vias pass through the at least one of the DBR stacks so as to connect the metal ring at the inner side of the at least one of the DBR stacks to an electrical contact on an outer side of the at least one of the DBR stacks.

Abstract: An optoelectronic device includes a semiconductor substrate with a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack. A second set of epitaxial layers formed over the first set defines a quantum well structure, and a third set of epitaxial layers, formed over the second set, defines an upper DBR stack. At least the third set of epitaxial layers is contained in a mesa having sides that are perpendicular to the epitaxial layers. A dielectric coating extends over the sides of at least a part of the mesa that contains the third set of epitaxial layers. Electrodes are coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure.

Abstract: An optoelectronic device includes a carrier substrate, with a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and including alternating first dielectric and semiconductor layers. A set of epitaxial layers is disposed over the lower DBR, wherein the set of epitaxial layers includes one or more III-V semiconductor materials and defines a quantum well structure and a confinement layer. An upper DBR stack is disposed over the set of epitaxial layers and includes alternating second dielectric and semiconductor layers. Electrodes are coupled to apply an excitation current to the quantum well structure.

Abstract: An optoelectronic device includes: (i) a semiconductor substrate doped with a first level of n-type dopants, (ii) a contact semiconductor layer disposed over the semiconductor substrate and doped with a second level of n-type dopants, larger than the first level, (iii) an upper distributed Bragg-reflector (DBR) stack disposed over the contact semiconductor layer and including alternating first and second epitaxial semiconductor layers having respective first and second indexes of refraction that differ from one another in a predefined wavelength band, (iv) a set of epitaxial layers disposed over the upper DBR, the set of epitaxial layers includes one or more III-V semiconductor materials and defines: (a) a quantum well structure, and (b) a confinement layer, and (v) a lower DBR stack disposed over the set of epitaxial layers, opposite the upper DBR, and including alternating dielectric and semiconductor layers.

Abstract: An optoelectronic device includes a carrier substrate, with a lower distributed Bragg-reflector (DBR) stack disposed on an area of the substrate and including alternating first dielectric and semiconductor layers. A set of epitaxial layers is disposed over the lower DBR, wherein the set of epitaxial layers includes one or more III-V semiconductor materials and defines a quantum well structure and a confinement layer. An upper DBR stack is disposed over the set of epitaxial layers and includes alternating second dielectric and semiconductor layers. Electrodes are coupled to apply an excitation current to the quantum well structure.

Abstract: An optoelectronic device includes a semiconductor substrate with a first set of epitaxial layers formed on an area of the substrate defining a lower distributed Bragg-reflector (DBR) stack. A second set of epitaxial layers formed over the first set defines a quantum well structure, and a third set of epitaxial layers, formed over the second set, defines an upper DBR stack. At least the third set of epitaxial layers is contained in a mesa having sides that are perpendicular to the epitaxial layers. A dielectric coating extends over the sides of at least a part of the mesa that contains the third set of epitaxial layers. Electrodes are coupled to the epitaxial layers so as to apply an excitation current to the quantum well structure.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, first and second stop layers are deposited on a first dielectric layer that covers a first metallization level. The second stop layer is selectively etched with respect to the first stop layer, and the first stop layer is selectively etched with respect to the first dielectric layer. A second dielectric layer and a third stop layer are deposited. The third stop layer is selectively etched with respect to the second dielectric layer, and the first and second dielectric layers are selectively etched with respect to the stop layers so as to form trenches in the second dielectric layer and holes in the first dielectric layer. Additionally, an integrated circuit is provided that includes first and second metallization levels. A dielectric layer is located between the metallization levels, and a first stop layer is located between the dielectric layer and the second metallization level.