Patents by Inventor Christopher A. Menkus
Christopher A. Menkus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230412183Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.Type: ApplicationFiled: June 15, 2023Publication date: December 21, 2023Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Publication number: 20230261666Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.Type: ApplicationFiled: March 27, 2023Publication date: August 17, 2023Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Patent number: 11716090Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.Type: GrantFiled: July 22, 2022Date of Patent: August 1, 2023Assignee: AyDee Kay LLCInventors: Christopher A. Menkus, Robert W. Kim
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Publication number: 20230238978Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.Type: ApplicationFiled: November 1, 2022Publication date: July 27, 2023Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Setu Mohta, Christopher A. Menkus, David Kang
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Patent number: 11632122Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.Type: GrantFiled: June 8, 2021Date of Patent: April 18, 2023Assignee: AyDeeKay LLCInventors: Christopher A. Menkus, Robert W. Kim
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Patent number: 11616511Abstract: An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.Type: GrantFiled: June 7, 2022Date of Patent: March 28, 2023Assignee: AyDeeKay LLCInventors: Christopher A. Menkus, Robert W. Kim
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Publication number: 20230013568Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.Type: ApplicationFiled: July 22, 2022Publication date: January 19, 2023Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Patent number: 11515883Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.Type: GrantFiled: May 17, 2021Date of Patent: November 29, 2022Assignee: AyDeeKay LLCInventors: Setu Mohta, Christopher A. Menkus, David Kang
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Publication number: 20220311448Abstract: An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.Type: ApplicationFiled: June 7, 2022Publication date: September 29, 2022Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Patent number: 11424753Abstract: An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.Type: GrantFiled: May 17, 2021Date of Patent: August 23, 2022Assignee: Ay Dee Kay LLCInventors: Robert W. Kim, Christopher A. Menkus
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Patent number: 11424752Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.Type: GrantFiled: May 17, 2021Date of Patent: August 23, 2022Assignee: AyDeeKay LLCInventors: Christopher A. Menkus, Robert W. Kim
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Publication number: 20220216880Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.Type: ApplicationFiled: June 8, 2021Publication date: July 7, 2022Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Publication number: 20220166440Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.Type: ApplicationFiled: May 17, 2021Publication date: May 26, 2022Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Setu Mohta, Christopher A. Menkus, David Kang
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Publication number: 20220149858Abstract: An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.Type: ApplicationFiled: May 17, 2021Publication date: May 12, 2022Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Publication number: 20220149854Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.Type: ApplicationFiled: May 17, 2021Publication date: May 12, 2022Applicant: AyDeeKay LLC dba Indie SemiconductorInventors: Christopher A. Menkus, Robert W. Kim
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Patent number: 7236115Abstract: A circuit for reducing the maximum magnitude of the total current on each of a plurality of buses for an amplifier stage in a folding analog to digital converter. Each amplifier stage bus couples multiple transconductance circuits to a load. Also, each of the transconductance circuits is configured to output a separate transconductance current to its respective bus. Separate current source circuits are configured to provide a separate source current locally at the output of each of the transconductance circuits such that substantially less than the full amount of each transconductance current reaches the respective bus.Type: GrantFiled: January 22, 2004Date of Patent: June 26, 2007Assignee: National Semiconductor CorporationInventors: Christopher A. Menkus, Robert Callaghan Taft
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Patent number: 7071670Abstract: A reference voltage is generated between a first node and a second node. A resistive element and a junction device are coupled in series between the first node and the second node. The junction device includes a junction between dissimilar materials, and has a negative temperature coefficient. First and second current sources route respective first and second bias currents to the resistive element and to the junction device. Routing is such that a resulting first branch current through the resistive element is generally not equal to a resulting second branch current through the junction device. The second bias current depends less on manufacturing process variation than the first bias current, and the second branch current can contain more of it, for less dependence on process. The second bias current can be generated by a source that uses the generated reference voltage as a reference.Type: GrantFiled: October 28, 2003Date of Patent: July 4, 2006Assignee: National Semiconductor CorporationInventors: Ols Hidri, Christopher A. Menkus
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Patent number: 7046179Abstract: An ADC circuit includes a multiplexer, a calibration circuit, one or more ADC banks, and a calibration ladder, all on an integrated circuit. The calibration resistor ladder is enabled during a calibration phase, and disabled during normal operation. When enabled, the calibration resistor ladder provides a calibration reference signal. Also, the multiplexer provides the calibration reference signal to one or more ADC banks during a calibration phase, and provides an analog input signal to the ADC banks otherwise. The calibration circuit is arranged to provide one or more adjustment signals to the ADC banks to calibrate the ADC banks in response to one or more comparator output signals from the ADC banks.Type: GrantFiled: March 30, 2004Date of Patent: May 16, 2006Assignee: National Semiconductor CorporationInventors: Robert C. Taft, Christopher A. Menkus, Maria R. Tursi, Ols Hidri, Andreas Tuechler, Valerie Pons
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Patent number: 6847320Abstract: A method and circuit for improving linearity of a folding or flash analog-digital-converter (ADC) circuit. Averaging resistors connect outputs of each of a bank of first pre-amplifiers. A series adjustment resistor is placed between each node connecting the output of a first bank pre-amplifier and the associated averaging resistor, and the input of each of a second bank pre-amplifier. An adjustment current is injected through the adjustment resistor during a calibration. A permanent value for adjustment current is determined such that an effect of offset errors is substantially minimized.Type: GrantFiled: March 30, 2004Date of Patent: January 25, 2005Assignee: National Semiconductor CorporationInventors: Robert C. Taft, Christopher A. Menkus
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Patent number: 6822600Abstract: A method and circuit for terminating a pre-amplification array for stable linearity of a folding or flash analog-digital-converter (ADC) circuit over a temperature range. Termination resistors with pre-selected temperature coefficients are coupled between outputs of a first and a last amplifier of an amplifier bank in an averaged pre-amplification stage and a termination voltage source. The termination resistors and the termination voltage provide a current that compensates temperature dependent changes in the current flowing from other amplifiers outputs towards the output of the first and last amplifiers stabilizing linearity when temperature changes. Multiple termination resistors with different temperature coefficients may be employed to better approximate the desired temperature coefficient for optimum performance.Type: GrantFiled: March 30, 2004Date of Patent: November 23, 2004Assignee: National Semiconductor CorporationInventors: Robert C. Taft, Christopher A. Menkus