Abstract: Zone selection logic in an area monitoring device increases the number of unique monitoring zone selections that can be selected using a limited number of discrete zone selection inputs, without compromising the safety critical operation of zone selection. The device monitors the logical state of each input in a set of individual inputs and recognizes each unique logical combination of zone selection inputs as a different zone selection. For example, each of two or more configured monitoring zones is associated with a different combinatorial zone selection pattern of asserted zone selection input signals. Correspondingly, a control circuit within the area monitoring device is configured to monitor the discrete zone selection inputs and activate a given one of the configured monitoring zones based on recognizing the associated combinatorial zone selection pattern of asserted zone selection signals.

Abstract: Zone selection logic in an area monitoring device increases the number of unique monitoring zone selections that can be selected using a limited number of discrete zone selection inputs, without compromising the safety critical operation of zone selection. The device monitors the logical state of each input in a set of individual inputs and recognizes each unique logical combination of zone selection inputs as a different zone selection. For example, each of two or more configured monitoring zones is associated with a different combinatorial zone selection pattern of asserted zone selection input signals. Correspondingly, a control circuit within the area monitoring device is configured to monitor the discrete zone selection inputs and activate a given one of the configured monitoring zones based on recognizing the associated combinatorial zone selection pattern of asserted zone selection signals.

Abstract: A data reduction circuit serves as a post-processor for digitized waveform data, providing reduced data sets for subsequent processing. Preferably, the data reduction circuit receives one or more potentially long sequences of digital waveform data and provides as output sets of sequence numbers corresponding to transitions in the digitized waveforms. In this manner, a processor concerned with the location of waveform transitions is relieved from the burden of processing the sequences just to identify the transition points. In some embodiments, the data reduction circuit cooperates with a waveform digitizer that produces digitized sequences of comparator waveforms in a laser-based distance measuring circuit. Transition points in the digitized waveform correspond to return reflections of emitted laser pulses and may be used to identify laser pulse flight time.

Abstract: A circuit generates a test signal useful in verifying the actual delay values of individual delay stages in a digital delay line. In general, the cumulative delay of the delay line defines a window in time having its zero point anchored to the beginning of the delay line. Successive delay stages correspond to successive time bins within the overall time window. The test signal shifts at a known, linear rate in time with respect to a reference signal, which is used to initiate a test cycle. The reference signal synchronizes sampling of the test signal to the beginning of the time window. Samples of the test signal are taken at sample points determined by the actual time delays in the successive delay stages. The observed distribution of test signal edges across the time window may be used to determine the actual delay intervals of the delay line.

Abstract: A circuit generates a test signal useful in verifying the actual delay values of individual delay stages in a digital delay line. In general, the cumulative delay of the delay line defines a window in time having its zero point anchored to the beginning of the delay line. Successive delay stages correspond to successive time bins within the overall time window. The test signal shifts at a known, linear rate in time with respect to a reference signal, which is used to initiate a test cycle. The reference signal synchronizes sampling of the test signal to the beginning of the time window. Samples of the test signal are taken at sample points determined by the actual time delays in the successive delay stages. The observed distribution of test signal edges across the time window may be used to determine the actual delay intervals of the delay line.

Abstract: A data reduction circuit serves as a post-processor for digitized waveform data, providing reduced data sets for subsequent processing. Preferably, the data reduction circuit receives one or more potentially long sequences of digital waveform data and provides as output sets of sequence numbers corresponding to transitions in the digitized waveforms. In this manner, a processor concerned with the location of waveform transitions is relieved from the burden of processing the sequences just to identify the transition points. In some embodiments, the data reduction circuit cooperates with a waveform digitizer that produces digitized sequences of comparator waveforms in a laser-based distance measuring circuit. Transition points in the digitized waveform correspond to return reflections of emitted laser pulses and may be used to identify laser pulse flight time.