Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

Abstract: Examples herein are related to a method and apparatus for determining dimensions of features in a patterned layer of a chip produced on a semiconductor production wafer. The production of the patterned layer includes a lithography step and an etching step, where the lithographic mask applied for producing the patterned layer is provided with one or more asymmetric marks. The position of printed and etched mark features is sensitive to lithographic and etch parameters. Changes in these positions are measured by overlay measurements, i.e. the measurement of the change in position of one mark relative to another. The obtained ‘pseudo’ overlay data are fitted to a parametric model, while characteristic feature dimensions are measured on a test wafer. The inverted model allows determination of feature dimensions on a production wafer. Application of the method on two different layers allows determination of edge placement errors between features of the two layers.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: A method is described for measuring a dimension on a substrate, wherein a target pattern is provided with a nominal characteristic dimension that repeats at a primary pitch of period P, and has a pre-determined variation orthogonal to the primary direction. The target pattern formed on the substrate is then illuminated so that at least one non-zero diffracted order is detected. The response of the non-zero diffracted order to variation in the printed characteristic dimension relative to nominal is used to determine the dimension of interest, such as critical dimension or overlay, on the substrate. An apparatus for performing the method of the present invention includes an illumination source, a detector for detecting a non-zero diffracted order, and means for positioning the source relative to the target so that one or more non-zero diffracted orders from the target are detected at the detector.

Abstract: A method is described for measuring a dimension on a substrate, wherein a target pattern is provided with a nominal characteristic dimension that repeats at a primary pitch of period P, and has a pre-determined variation orthogonal to the primary direction. The target pattern formed on the substrate is then illuminated so that at least one non-zero diffracted order is detected. The response of the non-zero diffracted order to variation in the printed characteristic dimension relative to nominal is used to determine the dimension of interest, such as critical dimension or overlay, on the substrate. An apparatus for performing the method of the present invention includes an illumination source, a detector for detecting a non-zero diffracted order, and means for positioning the source relative to the target so that one or more non-zero diffracted orders from the target are detected at the detector.

Abstract: A method is described for measuring a dimension on a substrate, wherein a target pattern is provided with a nominal characteristic dimension that repeats at a primary pitch of period P, and has a pre-determined variation orthogonal to the primary direction. The target pattern formed on the substrate is then illuminated so that at least one non-zero diffracted order is detected. The response of the non-zero diffracted order to variation in the printed characteristic dimension relative to nominal is used to determine the dimension of interest, such as critical dimension or overlay, on the substrate. An apparatus for performing the method of the present invention includes an illumination source, a detector for detecting a non-zero diffracted order, and means for positioning the source relative to the target so that one or more non-zero diffracted orders from the target are detected at the detector.

Abstract: A method is described for measuring a dimension on a substrate, wherein a target pattern is provided with a nominal characteristic dimension that repeats at a primary pitch of period P, and has a pre-determined variation orthogonal to the primary direction. The target pattern formed on the substrate is then illuminated so that at least one non-zero diffracted order is detected. The response of the non-zero diffracted order to variation in the printed characteristic dimension relative to nominal is used to determine the dimension of interest, such as critical dimension or overlay, on the substrate. An apparatus for performing the method of the present invention includes an illumination source, a detector for detecting a non-zero diffracted order, and means for positioning the source relative to the target so that one or more non-zero diffracted orders from the target are detected at the detector.

Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.

Abstract: A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies.

Abstract: A method of determining alignment error in electronic substrates comprises providing on a layer of a substrate a first contrasting set of elements forming a first grid pattern having a plurality of grid segments in the x and y directions. The method also includes providing nested within at least one of the first grid pattern segments, on the same or different layer of a substrate, a second contrasting set of elements forming a second grid pattern having a plurality of grid segments in the x and y directions. The method then includes determining the center of the first set of elements in the first grid pattern and determining the center of the second set of elements in the second grid pattern. The method then comprises comparing the centers of the first and second sets of elements and determining alignment error of the first and second grid patterns.

Abstract: A method of controlling imaging and process parameters in a lithographic process comprises providing a control pattern having an isolated feature with a pitch greater than twice a width of an individual feature, and exposing and developing a calibration resist layer with the control pattern design at a plurality of dose and focus settings. Width of the printed calibration control pattern feature is measured near the top and bottom of the resist layer thickness, and optimum dose and focus settings are then determined. Control patterns are printed at fixed exposure dose and focus settings on a production substrate, and width is measured near the top and bottom of the resist layer thickness. The widths of the production control pattern features are compared with the control pattern model parameters, and the imaging and process parameter settings in the production process are adjusted based on the comparison of the widths.

Abstract: A method of determining alignment error in electronic substrates comprises providing on a layer of a substrate a first contrasting set of elements forming a first grid pattern having a plurality of grid segments in the x and y directions. The method also includes providing nested within at least one of the first grid pattern segments, on the same or different layer of a substrate, a second contrasting set of elements forming a second grid pattern having a plurality of grid segments in the x and y directions. The method then includes determining the center of the first set of elements in the first grid pattern and determining the center of the second set of elements in the second grid pattern. The method then comprises comparing the centers of the first and second sets of elements and determining alignment error of the first and second grid patterns.