Abstract: Circuitry and logic are provided to a bus control module of a system bus of a computer system to inject the bus control module into, and win a system test master arbitration process initiated by a live inserted and successfully self tested CPU or I/O board. However, upon winning the system test master arbitration, the bus control module will inform the live inserted CPU or I/O board that it is not interested in having the CPU or I/O board in participating in system wide testing. In fact, the bus control module will not even initiate any system wide testing. As a result, CPU or I/O boards equipped with circuitry and logic to support certain required power on/reset testing protocol may be live inserted into the system without modifications, and without interruption to system operation.