Patents by Inventor Christopher D. Metcalf
Christopher D. Metcalf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10387332Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.Type: GrantFiled: April 11, 2017Date of Patent: August 20, 2019Assignee: Mellanox Technologies Ltd.Inventors: Christopher D. Metcalf, Bruce Edwards, Anant Agarwal, Chyi-Chang Miao, Patrick Robert Griffin
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Patent number: 10210092Abstract: Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.Type: GrantFiled: December 14, 2015Date of Patent: February 19, 2019Assignee: Mellanox Technologies, Ltd.Inventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
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Patent number: 10067796Abstract: Managing processes in a computing system comprising one or more cores includes generating an object in an operating system running on at least one core. A reference to the object is distributed to each of at least one and fewer than all of a plurality of processes to be executed on the at least one core. The operating system controls access to a resource such that processes to which the reference to the object was distributed have access to the resource and processes to which the reference to the object was not distributed do not have access to the resource.Type: GrantFiled: August 4, 2014Date of Patent: September 4, 2018Assignee: Mellanox Technologies Ltd.Inventor: Christopher D. Metcalf
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Patent number: 10037299Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.Type: GrantFiled: August 29, 2017Date of Patent: July 31, 2018Assignee: Mellanox Technologies Ltd.Inventors: Carl G. Ramey, Christopher D. Metcalf
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Patent number: 9213652Abstract: Managing data in a computing system comprising one or more cores includes: providing a cache in each of one or more of the cores that includes multiple storage locations; storing data of a first type of multiple types of data in a selected storage location of a first cache of a first core that is selected according to status information associated with the first cache, and updating the status information; and storing data of a second type of the multiple types of data in a storage location within a subset of fewer than all of the storage locations of the first cache and managing the status information to ensure that subsequent data of the second type received by the first core for storage in the first cache is stored in the storage location within the subset.Type: GrantFiled: September 20, 2010Date of Patent: December 15, 2015Assignee: Tilera CorperationInventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
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Patent number: 8799914Abstract: Managing processes in a computing system comprising one or more cores includes generating an object in an operating system running on at least one core. A reference to the object is distributed to each of at least one and fewer than all of a plurality of processes to be executed on the at least one core. The operating system controls access to a resource such that processes to which the reference to the object was distributed have access to the resource and processes to which the reference to the object was not distributed do not have access to the resource.Type: GrantFiled: September 20, 2010Date of Patent: August 5, 2014Assignee: Tilera CorporationInventor: Christopher D. Metcalf
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Patent number: 8738860Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.Type: GrantFiled: October 25, 2011Date of Patent: May 27, 2014Assignee: Tilera CorporationInventors: Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao, Christopher D. Metcalf, Bruce Edwards, Carl G. Ramey, Mark B. Rosenbluth, David M. Wentzlaff, Christopher J. Jackson, Ben Harrison, Kenneth M. Steele, John Amann, Shane Bell, Richard Conlin, Kevin Joyce, Christine Deignan, Liewei Bao, Matthew Mattina, Ian Rudolf Bratt, Richard Schooler
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Patent number: 8549249Abstract: Performing atomic operations in a computing system includes: acquiring a lock by performing a primary atomic operation that is directly supported in circuitry of the computing system on a first memory address in a memory of the computing system; accessing a second memory address in the memory of the computing system after the lock has been acquired; completing a secondary atomic operation based on accessing the second memory address; and releasing the acquired lock after the secondary atomic operation has been completed.Type: GrantFiled: September 20, 2010Date of Patent: October 1, 2013Assignee: Tilera CorporationInventors: Christopher D. Metcalf, Matthew Hostetter
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Patent number: 8539155Abstract: Managing cache memories in a computing system comprising multiple cores includes: assigning home cache locations for portions of data stored among caches in a group of caches of respective cores; accessing a first one of the portions of the cached data by sending an access request to a first home core of that first one of the portions of cached data; tracking a history of access for the first one of the portions of cached data; determining whether the tracked history of access for the first one of the portions of cached data exceeds or meets a predetermined condition, and re-assigning a home cache location of the first one of the portions of cached data from the first home core to a second, different home core when the predetermined condition is met or exceeded.Type: GrantFiled: September 20, 2010Date of Patent: September 17, 2013Assignee: Tilera CorporationInventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
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Patent number: 8521963Abstract: Managing data in a computing system comprising multiple cores includes: assigning a first set of data to caches within cores of a first subset of fewer than all of the cores in the computing system, and assigning a second set of data to caches within cores of a second subset of at least some remaining cores in the computing system not already assigned; and maintaining cache coherence among caches of respective cores in the first subset in response to data stored in at least one of the cores in the first subset being modified, and maintaining cache coherence among caches of respective cores in the second subset in response to data stored in at least one of the cores in the second subset being modified.Type: GrantFiled: September 20, 2010Date of Patent: August 27, 2013Assignee: Tilera CorporationInventors: Chyi-Chang Miao, Christopher D. Metcalf, Ian Rudolf Bratt, Carl G. Ramey
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Patent number: 8392661Abstract: Managing data in a computing system comprising a plurality of cores includes assigning home cache locations of at least a first type of data associated with a first process executing on a first core to respective caches of one or more of the plurality of cores. Cores other than a home core, whose cache includes a home cache location for given cached data, access the given cached data by communicating with the home core. Home cache locations of at least a second type of data associated with the first process are assigned to a local cache of the first core. In response to migrating the first process to execute on a second core, home cache locations of the second type of data associated with the first process are re-assigned to a local cache of the second core.Type: GrantFiled: September 20, 2010Date of Patent: March 5, 2013Assignee: Tilera CorporationInventor: Christopher D. Metcalf
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Patent number: 8327187Abstract: Managing processes in a computing system comprising one or more cores includes receiving a request for a first process on a first core to execute with at least one predetermined task of an operating system disabled on the first core. In response to the request, the operating system determines whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core. The operating system grants the request or rejects the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.Type: GrantFiled: September 20, 2010Date of Patent: December 4, 2012Assignee: Tilera CorporationInventor: Christopher D. Metcalf
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Patent number: 7827154Abstract: A method and mechanism for diagnosing application failures. An executable application is augmented with code which generates a list of components, as well as version information, utilized by the application. Also created is data which associates application components with applications which utilize those components. The list of components, version information, and association data are stored in a database and updated each time the application is run. In response to detecting a failure of the application, a database query is generated which returns a list of components utilized by the failed application. By comparing the date that application components changed to the date the application was last successfully run, a high priority list of components which changed since the last successful run may be generated. Diagnosis of the application failure may then begin with components in the high priority list.Type: GrantFiled: October 5, 2004Date of Patent: November 2, 2010Assignee: Symantec Operating CorporationInventors: Michael P. Spertus, David A. Stuckmann, Richard Schooler, Christopher D. Metcalf
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Patent number: 7805717Abstract: A system and method for instrumenting program instructions. A processing system includes a compiler and a profiler. The compiler is configured to notify the profiler of a compilation event corresponding to first program instructions. In response to detecting the event, the profiler is configured to intercept compilation of the first program instructions, determine whether an instrumented version of the first program instructions is currently available, instruct the compiler to compile the instrumented version of the first program instructions if available, and retrieve and instrument the first program instructions if not available. The profiler may maintain an instrumentation cache for storing instrumented versions of program instructions. The instrumentation cache may further include metadata which identifies portions of program code which have been instrumented and their location. The profiler may generally instrument program instructions once during the resident life of a corresponding application.Type: GrantFiled: October 17, 2005Date of Patent: September 28, 2010Assignee: Symantec Operating CorporationInventors: Michael P. Spertus, Christopher D. Metcalf, Gadi Wolfman
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Patent number: 7739689Abstract: Methods and systems are provided for internal monitoring of applications. A distributed management framework may comprise a plurality of applications and application servers, wherein each of the applications is configured to make function calls to standard programming functions. The function calls to the standard programming functions are intercepted. The function calls are routed to alternative implementations of the standard programming functions, and the alternative implementations are used to collect availability metrics for the plurality of applications. Manager threads may be used for internal monitoring of application execution. Applications may be modified with additional instructions to monitor program execution and automatically generate output comprising an execution history.Type: GrantFiled: February 27, 2004Date of Patent: June 15, 2010Assignee: Symantec Operating CorporationInventors: Michael P. Spertus, Christopher D. Metcalf, Richard Schooler, David A. Stuckmann
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Patent number: 7725882Abstract: A system and method for managing the environment of software processes in a computer system. A computer system comprises a processor and at least one process environment comprising one or more environment variables. The processor executes one or more processes, intercepts the launch of a process, sets at least one environment variable to a first value, and continues the launch of the process. Setting the environment variable may enable a profiler process. The processor may set at least one environment variable for the process to a value which is chosen irrespective of a value of the environment variable of a parent process of the process. Further, the processor may set at least one environment variable for the process to a default value if a data repository does not contain an entry that has an identification which corresponds to the process.Type: GrantFiled: September 30, 2005Date of Patent: May 25, 2010Assignee: Symantec Operating CorporationInventors: Michael P. Spertus, Christopher D. Metcalf, Gadi Wolfman
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Patent number: 7299384Abstract: A method and mechanism for managing dynamically allocated memory. Portions of memory which are available for allocation have additional information stored in association with each portion which indicates whether the portion has been previously identified as being prematurely freed. In addition, a checksum is stored with each portion of memory. In response to a request for deallocation of a portion of memory, the portion of memory is not deallocated if it is identified as having been prematurely freed. Otherwise, the a checksum is calculated for the portion and it is freed. In response to an allocation request, a candidate portion of memory is identified for allocation and a checksum is calculated for the candidate portion. If the calculated checksum does not match a checksum previously stored for the candidate portion, the portion is identified as having been prematurely freed and is not returned for allocation.Type: GrantFiled: August 17, 2004Date of Patent: November 20, 2007Assignee: Symantec Operating CorporationInventors: Gustavo Rodriguez-Rivera, Michael P. Spertus, Charles Fiterman, Jim Polubinski, Brian Day, Daryl Hoyt, Christopher D. Metcalf
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Patent number: 7296261Abstract: A method for determining changed code in a second program binary relative to a first or baseline program binary, where the second program is a different version of the first program, includes translating, responsive to symbol tables and/or control flow representations, machine addresses of both program binaries to symbols. The first and second program binaries are disassembled using the translated symbols. Differences between the two resulting disassemblies are determined, and a list of the differences is created. Differences between the program binaries can be determined by textually comparing the disassemblies, or alternatively, by determining the differences between the control flow representations of the programs. The list of differences can be presented to a user, or alternatively, can be passed to another process for further processing, such as test coverage analysis, code change analysis, or failure analysis, among other analyses.Type: GrantFiled: June 4, 2004Date of Patent: November 13, 2007Assignee: VERITAS Operating CorporationInventors: Emmett Witchel, Christopher D. Metcalf, Andrew E. Ayers
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Publication number: 20040221270Abstract: A method for determining changed code in a second program binary relative to a first or baseline program binary, where the second program is a different version of the first program, includes translating, responsive to symbol tables and/or control flow representations, machine addresses of both program binaries to symbols. The first and second program binaries are disassembled using the translated symbols. Differences between the two resulting disassemblies are determined, and a list of the differences is created. Differences between the program binaries can be determined by textually comparing the disassemblies, or alternatively, by determining the differences between the control flow representations of the programs. The list of differences can be presented to a user, or alternatively, can be passed to another process for further processing, such as test coverage analysis, code change analysis, or failure analysis, among other analyses.Type: ApplicationFiled: June 4, 2004Publication date: November 4, 2004Inventors: Emmett Witchel, Christopher D. Metcalf, Andrew E. Ayers
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Patent number: 6748584Abstract: A method for determining changed code in a second program binary relative to a first or baseline program binary, where the second program is a different version of the first program, includes translating, responsive to symbol tables and/or control flow representations, machine addresses of both program binaries to symbols. The first and second program binaries are disassembled using the translated symbols. Differences between the two resulting disassemblies are determined, and a list of the differences is created. Differences between the program binaries can be determined by textually comparing the disassemblies, or alternatively, by determining the differences between the control flow representations of the programs. The list of differences can be presented to a user, or alternatively, can be passed to another process for further processing, such as test coverage analysis, code change analysis, or failure analysis, among other analyses.Type: GrantFiled: December 29, 1999Date of Patent: June 8, 2004Assignee: Veritas Operating CorporationInventors: Emmett Witchel, Christopher D. Metcalf, Andrew E. Ayers