Patents by Inventor Christopher D. Shuler
Christopher D. Shuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126457Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.Type: ApplicationFiled: December 11, 2023Publication date: April 18, 2024Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
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Patent number: 11893251Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.Type: GrantFiled: August 31, 2021Date of Patent: February 6, 2024Assignee: Apple Inc.Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
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Patent number: 11704245Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.Type: GrantFiled: August 31, 2021Date of Patent: July 18, 2023Assignee: Apple Inc.Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
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Publication number: 20230062917Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
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Publication number: 20230067307Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
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Patent number: 11537538Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.Type: GrantFiled: April 27, 2021Date of Patent: December 27, 2022Assignee: Apple Inc.Inventors: Harshavardhan Kaushikkar, Christopher D. Shuler, Srinivasa Rangan Sridharan, Yu Zhang, Kaushik Kannan, Deniz Balkan
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Publication number: 20210303486Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.Type: ApplicationFiled: April 27, 2021Publication date: September 30, 2021Inventors: Harshavardhan Kaushikkar, Christopher D. Shuler, Srinivasa Rangan Sridharan, Yu Zhang, Kaushik Kannan, Deniz Balkan
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Patent number: 11016913Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.Type: GrantFiled: March 30, 2020Date of Patent: May 25, 2021Assignee: Apple Inc.Inventors: Harshavardhan Kaushikkar, Christopher D. Shuler, Srinivasa Rangan Sridharan, Yu Zhang, Kaushik Kannan, Deniz Balkan
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Patent number: 10298511Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.Type: GrantFiled: August 24, 2016Date of Patent: May 21, 2019Inventors: Manu Gulati, Christopher D. Shuler, Benjamin K. Dodge, Thejasvi M. Vijayaraj, Harshavardhan Kaushikkar, Yang Yang, Rong Z. Hu, Srinivasa R. Sridharan, Wolfgang H. Klingauf, Neeraj Parik
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Publication number: 20180063016Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.Type: ApplicationFiled: August 24, 2016Publication date: March 1, 2018Inventors: Manu Gulati, Christopher D. Shuler, Benjamin K. Dodge, Thejasvi M. Vijayaraj, Harshavardhan Kaushikkar, Yang Yang, Rong Z. Hu, Srinivasa R. Sridharan, Wolfgang H. Klingauf, Neeraj Parik