Abstract: A configurable phased array tile is disclosed including an aperture assembly having a plurality of aperture assembly connectors, a backplane assembly having a plurality of backplane assembly connectors, and a plurality of vertical transmit cards mounted to a corresponding first plurality of aperture assembly connectors and a corresponding first plurality of backplane assembly connectors. The plurality of vertical transmit cards each include a plurality of transmit channels including at least one high power transmit amplifier for powering at least one radiating element mounted to the aperture assembly.

Abstract: A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.

Abstract: An apparatus and method for detecting radio frequency transmit power levels produced by a power amplifier of a wireless device is described. In one exemplary apparatus implementation, the apparatus includes a power amplifier, an antenna switch and a power amplifier detector. The power amplifier is configured to amplify a transmit signal at a desired power level. An antenna switch, is located between the power amplifier and an antenna, and is configured to switch the antenna from a receive mode to a transmit mode and vice versa. A power amplifier detector is connected to the antenna switch. The power amplifier detector is configured to receive a leakage signal from the antenna switch as a basis to detect the power level of the transmit signal.

Abstract: An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.

Abstract: An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.

Abstract: In accordance with the present invention, a quadrature hybrid circuit is provided comprising a first spiral inductor and a second spiral inductor separated by an insulating layer to provide all necessary capacitances intrinsically. Further, a vector modulator circuit is provided that incorporates a plurality of quadrature hybrid circuits on a MMIC contained within a chip scale package.

Abstract: An apparatus and method for transmitting signal, the apparatus comprising a front end telecommunications module including a power amplifier, a matching circuit coupled to the power amplifier, and a filter coupled to the matching circuit, such that a signal received by the power amplifier is transmitted to the filter through the matching circuit. The telecommunications module provides quad-band capability in a compact design.

Abstract: In accordance with the present invention, a quadrature hybrid circuit is provided comprising a first spiral inductor and a second spiral inductor separated by an insulating layer to provide all necessary capacitances intrinsically. Further, a vector modulator circuit is provided that incorporates a plurality of quadrature hybrid circuits on a MMIC contained within a chip scale package.

Abstract: An electronic SPDT switch (1) has, a series FET (9) in a first circuit arm (4) between a common port (2) and a first port (3), a shunt FET (10) in a second circuit arm (6) between the common port (2) and a second port (5), the shunt FET (10) being isolated 90 degrees or 1/4 wavelength from the common port (2), a source applying pull-up voltage to sources of respective FETs (9, 10) and to the common port (2), to provide a connection of the common port (2) with said second port (5), a source applying a first control voltage of opposite logic state to said gates, and the FETs (9, 10) being depletion mode FETs that conduct at a zero sum of said bias voltage and said control voltage, and that conduct when DC power is interrupted, to provide a connection of the common port (2) with the first port (3).