Abstract: The present invention is a data word extraction circuit that receives n data words DW.sub.x (for x equal 0 through n-1), where each of the data words DW.sub.x having m bit positions BP.sub.y (for y=0 through m-1). The circuit provides at least one of the data words DW.sub.x to an extraction circuit output responsive to an extraction indicator signal. Specifically, a group of data selector elements DSE.sub.y, each corresponding to a separate one of the bit positions BP.sub.y in the received data words. Each data selector element includes a data output DO.sub.y and a plurality of data inputs DI.sub.x. Each data input DI.sub.x is connected to receive a bit from the bit position BP.sub.y to which the data selector element DSE.sub.y corresponds, of a data word DW.sub.x to which the data input DI.sub.x corresponds. A select input is responsive to the extraction indicator signal such that the data selector element DSE.sub.y provides, at the data output, the bit received at one of the data inputs DI.sub.

Abstract: A method and apparatus for fault testing a pipelined processor. In test mode, the stage registers are reconfigured as multiple input shift registers by switching in a few exclusive-OR gates. Also, the execute stage is prevented from executing any instructions. A unique sequential test sequence of instructions are run through the processor at normal speed. It is known that a particular test sequence (and thus a unique sequential input pattern to the MISR, assuming no faults) will result in a unique signature pattern existing in the MISR at the end of the sequence. If the signature pattern is not found in the MISR at the end of the test sequence, then it is known that a fault exists on the chip.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: An input/output circuit for increasing immunity to voltage spikes from voltage supplies is provided. The circuit includes a first pair of transistors each having their drains connected to an output terminal and their sources connected to voltage supplies. A mechanism is connected to electrically separated voltage supplies to alternately turn on one of the first pair of transistors responsive to an input signal. A transistor is utilized to provide feedback to limit the rise in a ground voltage supply as occurs during ground bounce.

Abstract: A circuit designates the values of an M bit first pointer and of an N+M bit second pointer. A first register circuit network holds the M bit first pointer, and a second register circuit network into holds an M bit portion of the N+M bit second pointer. A third register circuit network holds the remaining N bit portion of the N+M bit second pointer. A combiner circuit network, connected to receive the M bit first pointer from the first register circuit network, combines the received M bit first pointer with an externally provided data element length value to generate a new M bit first pointer. The combiner circuit network selectively generates a carry signal. The new M bit first pointer is selectively provided for loading into the first register circuit network and for loading into the second register circuit network as the M bit portion of the N+M bit portion of the second pointer.

Abstract: A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

Abstract: An availability status indicator circuit simultaneously indicates which of N circular buffer cells (CBC.sub.x, for x=0 through N-1) are available for access. N cell status circuits are provided that correspond to the separate circular buffer cells. Each cell status circuit includes an output terminal at which a cell availability status signal is provided to indicate the availability status of the corresponding circular buffer cell. A first input terminal of the cell status circuit is connected to receive the cell availability status signal from the previous cell status circuit.

Abstract: A demand-based clocking circuit generates a demand-based gated clock signal. A latch circuit data input receives an enable signal. A clock input receives a first periodic input clock signal. A latch circuit data output provides a shifted enable signal that transitions from an inactive logic state to an active logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the inactive to the active logic state. The shifted enable signal transitions from the active to the inactive logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the active to the inactive logic state.

Abstract: A partitioned decoder circuit responds to an address signal supplied at a decoder circuit input by providing a result data signal that corresponds to the address signal. Selection signal decoder circuitry asserts one or more of a plurality of decoder enable signals based upon the value of a decoder selection signal. A plurality of decoder circuit elements are each connected to receive a separate one of the asserted decoder enable signals. Each decoder circuit element includes a first clock input coupled to receive a precharge clock signal, an address input coupled to receive the address signal, address latching circuitry that latches the address signal in response to a polarity transition of the precharge clock signal, and a second clock input. Significantly, gated discharge clock signal generation circuitry of each decoder circuit element generates a gated discharge clock signal in response to the asserted decoder enable signal. The gated discharge clock signal is provided to the second clock input.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.

Abstract: A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch.