Patents by Inventor Christopher G. Wieduwilt
Christopher G. Wieduwilt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210158888Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: Christopher G. Wieduwilt, James S. Rehmeyer, Seth A. Eichmeyer
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Patent number: 11017879Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.Type: GrantFiled: December 20, 2019Date of Patent: May 25, 2021Assignee: Micron Technology, Inc.Inventors: James S. Rehmeyer, Christopher G. Wieduwilt, George Raad, Seth Eichmeyer, Dean Gans
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Patent number: 11011250Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.Type: GrantFiled: February 28, 2020Date of Patent: May 18, 2021Assignee: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Alan J. Wilson
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Publication number: 20210083909Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Christopher G. Wieduwilt, Jason Johnson
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Patent number: 10937517Abstract: An exemplary memory includes a memory cell array configured to store a plurality of data bits each associated with a respective column plane, and an input/output circuit including a compression circuit configured to provide error data based on a comparison between a bit of the plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array with which the bit is associated. The compression circuit is further configured to encode a column plane error code based on the error data for provision to a data terminal.Type: GrantFiled: November 15, 2019Date of Patent: March 2, 2021Assignee: Micron Technology, Inc.Inventors: Eric J. Rich-Plotkin, Christopher G. Wieduwilt, Boon Hor Lam, Greg S. Hendrix, Shawn M. Hilde, Jiyun Li, Dennis G. Montierth
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Publication number: 20210055981Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.Type: ApplicationFiled: August 20, 2019Publication date: February 25, 2021Applicant: Micron Technology, Inc.Inventors: Daniel S. Miller, Kevin G. Werhane, Yoshinori Fujiwara, Christopher G. Wieduwilt, Jason M. Johnson, Minoru Someya
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Patent number: 10923172Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.Type: GrantFiled: March 9, 2020Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Jason M. Johnson, Christopher G. Wieduwilt, Daniel S. Miller, Yoshinori S. Fujiwara
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Patent number: 10855495Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: GrantFiled: September 18, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Jason Johnson
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Publication number: 20200265912Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.Type: ApplicationFiled: February 28, 2020Publication date: August 20, 2020Inventors: Christopher G. Wieduwilt, Alan J. Wilson
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Publication number: 20200243155Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: ApplicationFiled: April 17, 2020Publication date: July 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Publication number: 20200211635Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Applicant: Micron Technology, Inc.Inventors: Jason M. Johnson, Christopher G. Wieduwilt, Daniel S. Miller, Yoshinori S. Fujiwara
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Patent number: 10643734Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: GrantFiled: June 27, 2018Date of Patent: May 5, 2020Assignee: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Patent number: 10600496Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.Type: GrantFiled: October 18, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Alan J. Wilson
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Patent number: 10593392Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for timing refresh operations in a memory device. An apparatus may include an oscillator that provides a periodic signal to one or more refresh timer circuits. Each of the refresh timer circuits is associated with a respective memory bank in the memory device. The refresh timer may include a counter block and a control logic block. The control logic block may gate the periodic signal to the counter block. The counter block may count the row active signal time and the row precharge time. The counter signals may be used by the control logic block to output a number of pumps of a refresh operation.Type: GrantFiled: December 19, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Jason M. Johnson, Christopher G. Wieduwilt, Daniel S. Miller, Yoshinori S. Fujiwara
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Publication number: 20200036560Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: ApplicationFiled: September 18, 2019Publication date: January 30, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Christopher G. Wieduwilt, Jason Johnson
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Patent number: 10530613Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: GrantFiled: September 28, 2018Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Jason Johnson
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Publication number: 20200005885Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.Type: ApplicationFiled: June 27, 2018Publication date: January 2, 2020Applicant: Micron Technology, Inc.Inventors: Christian N. Mohr, Gregg D. Wolff, Christopher G. Wieduwilt, C. Omar Benitez, Dennis G. Montierth
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Publication number: 20190036740Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Applicant: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Jason Johnson
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Patent number: 10193711Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: GrantFiled: June 22, 2017Date of Patent: January 29, 2019Assignee: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Jason Johnson
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Publication number: 20180375692Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Applicant: Micron Technology, Inc.Inventors: Christopher G. Wieduwilt, Jason Johnson