Abstract: A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.

Abstract: A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.

Abstract: A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using the inner error correction code of the encoded data followed by the outer error correction code of the encoded data if it is determined that the correction capacity of the outer error correction code is exceeded. Additionally, if it is determined that the correction capacity of the outer error correction code is exceed after recovering the data using the inner error correction code, the nonvolatile memory storage module may perform a redundant array of independent disks (RAID) operation to recover the data.

Abstract: A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.

Abstract: In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.

Abstract: A syndrome generator generates odd syndromes of a sequence of syndromes and stores the odd syndromes in registers. A syndrome sequencer identifies the register storing the next syndrome of the sequence of syndromes, reads the syndrome from the register, and outputs the syndrome to a sequential polynomial generator. Further, the syndrome sequencer generates an even syndrome by squaring the syndrome read from the register and writes the even syndrome into the same register. Moreover, the syndrome sequencer outputs each syndrome of the sequence of syndromes in sequential order. The sequential polynomial generator generates a locator polynomial in a number of iterations based on the sequence of syndromes received from the syndrome sequencer.

Abstract: A deskew module of a receiver includes deskew units, each of which includes a data aggregation module for selecting a data rate for receiving symbols of a corresponding data stream. The deskew unit includes a data aggregation module that aggregates a predetermined number of the symbols in one or more clock cycles of a clock signal based on the data rate. The predetermined number of symbols is the same for each data rate selectable by the data aggregation module. The data aggregation module outputs the aggregated symbols to a deskew buffer of the deskew unit in a clock cycle of a clock signal. The deskew buffer deskews symbols received from the data aggregation module and outputs the deskewed symbols.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a deskew unit for each data stream, each of which includes multiple data queues. Each of the deskew units stores symbols of the data stream received by the deskew unit into the data queues of the data unit by distributing the symbols among the data queues. The deskew unit aligns data symbols across the data streams by deskewing symbols stored in the data queues of the deskew units based on skip ordered sets in the deskew units. Moreover, the receiver may deskew more than one symbol per clock cycle.

Abstract: An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correction code generator includes logic circuits for generating check bits in the error correction code. The error detector includes logic circuits for identifying any data bits of the data unit having a bit error based on the error correction code. The logic circuits in the error correction code generator and the error detector are derived from group codes separated from each other by a hamming distance and having a same population count. The error correction code system may also include an error corrector for correcting error bits in the data unit.

Abstract: A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a data buffer for each data stream that stores a minimal skip ordered set based on the skip ordered set in the data stream received by the data buffer. Each of the minimal skip ordered sets has a same number of symbols. Additionally, each buffer stores data of the data stream received by the data buffer. The receiver aligns the data among the data buffers based on the minimal skip ordered sets in the data buffers and outputs the aligned data. In this way, the receiver deskews the data in the data streams.

Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.

Abstract: A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a data selector circuit that is enabled to select the content of an address register in an array of address registers, and a comparator electrically coupled to the data selector circuit and enabled to take a first input from the data selector circuit and target address as a second input from a communication packet. The method includes receiving the target address, seeking and locating a matching address in an array of base address registers, directing the packet to the port associated with the matching address, determining the target address to be a valid address by comparing the target address with a limit address associated with the matching base address, and nullifying the match if the target address is greater than the limit address.

Abstract: A method and device for handling catastrophic switch routing errors. Upon receiving a communication packet in a packet switching device, a port in the switching device is matched with the destination address of the communication packet and a routing code is generated to direct routing of the communication packet internally to the packet switching device. The routing code is analyzed to determine whether a catastrophic routing condition exists in the routing code. If no catastrophic routing condition exists, the routing is executed. However, when there is a catastrophic routing condition, execution of the routing of the communication packet is prevented.

Abstract: A system and method in accordance with the invention produces an ECC code that is transmitted in the y-bit domain along with data is converted from a native x-bit domain to the y-bit domain. Such a system and method provides a representation of an ECC code that is part of a transmitted serial stream that allows clock recovery and that can use parity checking or other method to verity the integrity of the transmitted ECC code itself.

Abstract: A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address registers having a base address, and control logic circuitry electrically coupled to the array of shadow registers and to the array of base address registers with the control logic circuitry being operable, when it receives a configuration command, to implement a method, for reconfiguring the contents of the array of base address registers, including: inserting a new base address from the configuration command into a shadow register in the array of shadow registers, sorting the array of shadow registers into a predetermined order, and then copying the contents of the array of shadow registers into the array of base address registers.

Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.

Abstract: A device and method are disclosed for performing a limit address check validation in a switching device. The device includes a multiplexer that is enabled to select content from a base address register in an array of base address registers, a comparator enabled compare a base address in the content with a target address from a packet, and a comparator enabled to concurrently compare a limit address in the content with the target address and the output of the limit address comparator. The method includes receiving the target address, locating a matching base address in an array of base address registers, concurrently comparing the target address with a limit address associated with the matching base address, and indicating if said target address is not valid.

Abstract: A base address matching device and method are disclosed. In a switching device having a plurality of input/output ports, a routing device has been described that has an array of registers in which each register holds content associating an address with one of the input/output ports in the switching device and elements of the content in the array of registers are pre-sorted into a specified order, and an address matching element that has a plurality of comparators that are electrically coupled to selected registers in the array of registers. The base address matching element is able to select a matching address from the content of the array of registers and to direct a communication packet to one of the ports in the switch by matching the target address in the packet to an address in the content of the register in the array of registers associated with the port.

Abstract: In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards.

Abstract: A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N? switch matrix is programmably made to operate as if it were a plurality of S×S? virtual switch slices, where S<N and S?<N?. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for.