Patents by Inventor Christopher J. Case
Christopher J. Case has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230098098Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.Type: ApplicationFiled: September 28, 2021Publication date: March 30, 2023Applicant: Xilinx, Inc.Inventors: Adam P. Donlin, Kyle Corbett, Christopher J. Case
-
Patent number: 11610042Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.Type: GrantFiled: September 28, 2021Date of Patent: March 21, 2023Assignee: Xilinx, Inc.Inventors: Adam P. Donlin, Kyle Corbett, Christopher J. Case
-
Patent number: 11204747Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).Type: GrantFiled: October 17, 2017Date of Patent: December 21, 2021Assignee: XILINX, INC.Inventors: Jindrich Zejda, Elliott Delaye, Yongjun Wu, Aaron Ng, Ashish Sirasao, Khang K. Dao, Christopher J. Case
-
Patent number: 10802995Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.Type: GrantFiled: July 26, 2018Date of Patent: October 13, 2020Assignee: Xilinx, Inc.Inventors: Sarabjeet Singh, Hem C. Neema, Sonal Santan, Khang K. Dao, Kyle Corbett, Yi Wang, Christopher J. Case
-
Publication number: 20200081850Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.Type: ApplicationFiled: July 26, 2018Publication date: March 12, 2020Applicant: Xilinx, Inc.Inventors: Sarabjeet Singh, Hem C. Neema, Sonal Santan, Khang K. Dao, Kyle Corbett, Yi Wang, Christopher J. Case
-
Patent number: 8769449Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.Type: GrantFiled: February 8, 2013Date of Patent: July 1, 2014Assignee: Xilinx, Inc.Inventors: Adam P. Donlin, Biping Wu, Kyle Corbett, Nabeel Shirazi, Shay P. Seng, Amit Kasat, Srinivas Beeravolu, Khang K. Dao, Jeffrey H. Seltzer, Christopher J. Case
-
Patent number: 6470961Abstract: A condenser, radiator and fan assembly module for providing modular installation and simplified individual servicing of the components thereof. The module includes a condenser, a radiator, a fan assembly, and a module frame having a set of channels for respectively receiving therein each of the condenser, radiator and fan assembly. Each of the condenser, the radiator and the fan assembly are slidably received into its respective channel. A floor of the module frame may be disassembled to facilitate individual sliding removal of any of the condenser, radiator or fan assembly. To facilitate sliding installation and removal of the radiator, the coolant inlet fitting and the coolant outlet fitting are each threadably engaged into a respective threaded opening in the tank of the radiator.Type: GrantFiled: January 8, 2002Date of Patent: October 29, 2002Assignee: General Motors CorporationInventor: Christopher J. Case
-
Patent number: 6217427Abstract: A tool for the linear polishing of substrates includes an endless belt of continuous strength wrapped substantially as a helix of predetermined length and width with a 180 degree twist along the length to increase by a factor of 2× the time interval between which belt changes need to be made because of wear-and-tear, significantly reducing the costs associated with the polishing because of reduced down time. In a preferred embodiment for the chemical-mechanical polishing of silicon wafer substrates used in fabricating integrated circuits, the endless belt is constructed as a Mobius strip of a rubberized, urethane composition to be flexible, but yet strong enough to withstand the applied pressure between the polishing belt and the substrate.Type: GrantFiled: April 6, 1999Date of Patent: April 17, 2001Assignee: Agere Systems Inc.Inventors: Christopher J. Case, Carlye B. Case
-
Patent number: 5008217Abstract: Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.Type: GrantFiled: June 8, 1990Date of Patent: April 16, 1991Assignee: AT&T Bell LaboratoriesInventors: Christopher J. Case, Kin P. Cheung, Ruichen Liu, Ronald J. Schutz, Richard S. Wagner
-
Patent number: D1020510Type: GrantFiled: September 19, 2019Date of Patent: April 2, 2024Assignee: GENTEX CORPORATIONInventors: Michael G. Hendricks, Christopher B. Case, James E. Marsh, Gregory A. Herrema, Paul K. Postma, Douglas J. Newhouse
-
Patent number: D1027510Type: GrantFiled: April 29, 2021Date of Patent: May 21, 2024Assignee: Target Brands, Inc.Inventors: Rachel R. Riddle, William Y. Stafford, Joseph R. Stukenberg, Christopher S. Case, Jeremiah J. Albrecht, Bill R. Landgraf, James B. Voigt