Patents by Inventor Christopher J. Pass
Christopher J. Pass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200075088Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.Type: ApplicationFiled: August 28, 2018Publication date: March 5, 2020Applicant: Intel CorporationInventors: Yue-Song He, Rusli Kurniawan, Richard G. Smolen, Christopher J. Pass, Andy L. Lee, Jeffrey T. Watt, Anwen Liu, Alok Nandini Roy
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Patent number: 10573375Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.Type: GrantFiled: August 28, 2018Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Yue-Song He, Rusli Kurniawan, Richard G. Smolen, Christopher J. Pass, Andy L. Lee, Jeffrey T. Watt, Anwen Liu, Alok Nandini Roy
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Patent number: 10447275Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.Type: GrantFiled: August 29, 2018Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Andy L. Lee, Richard G. Smolen, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He
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Patent number: 10269426Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.Type: GrantFiled: June 15, 2017Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Richard G. Smolen, Rusli Kurniawan, Yue-Song He, Andy L. Lee, Jeffrey T. Watt, Christopher J. Pass
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Publication number: 20190020344Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.Type: ApplicationFiled: August 29, 2018Publication date: January 17, 2019Inventors: Andy L. Lee, Richard G. Smolen, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He
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Publication number: 20180366192Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.Type: ApplicationFiled: June 15, 2017Publication date: December 20, 2018Applicant: Intel CorporationInventors: Richard G. Smolen, Rusli Kurniawan, Yue-Song He, Andy L. Lee, Jeffrey T. Watt, Christopher J. Pass
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Patent number: 10090840Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.Type: GrantFiled: June 29, 2017Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Andy L. Lee, Richard G. Smolen, Rusli Kurniawan, Jeffrey T. Watt, Christopher J. Pass, Yue-Song He
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Patent number: 10037992Abstract: A transistor device is provided. The transistor device includes a group of fins formed in a substrate, where the group of fins comprises at least one enabled fin and at least one disabled fin. Each of the fins has first and second fin portions. The first fin portion encompasses a drain region and the second fin portion of the fins encompasses a source region. These two regions are separated by a channel region. A gate structure is formed over the fins and channel region and in between the first fin portion and the second fin portion of the fins. The transistor device further includes a conductive structure. The conductive structure shorts the first fin portion of the at least one disabled fin to the second fin portion of the at least one disabled fin.Type: GrantFiled: December 22, 2014Date of Patent: July 31, 2018Assignee: Altera CorporationInventors: Zhiyuan Wu, Ning Cheng, Christopher J. Pass
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Patent number: 8912104Abstract: An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.Type: GrantFiled: March 14, 2011Date of Patent: December 16, 2014Assignee: Altera CorporationInventors: Deepa Ratakonda, Christopher J. Pass, Che Ta Hsu, Fangyun Richter, Wilson Wong
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Patent number: 8519403Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.Type: GrantFiled: February 4, 2011Date of Patent: August 27, 2013Assignee: Altera CorporationInventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
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Patent number: 7883946Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.Type: GrantFiled: May 8, 2008Date of Patent: February 8, 2011Assignee: Altera CorporationInventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
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Patent number: 6956165Abstract: An electronic package is disclosed with an underfill with multiple areas of different stiffness and a method of constructing same. An underfill shell region that contacts the chip and the substrate is stiffer than an underfill build region that does not contact either the chip or the substrate. The variation in stiffness may be achieved using materials in the shell that include more filler and/or less solvents than the materials in the bulk region. The underfill may also be composed of a single material with an adhesion to the chip and substrate that is stronger than the material's internal cohesion (e.g., a long chain polymer with an active carboxyl group at the end of the chain). This can be achieved by exposing the chip and substrate surfaces to a curing substance (e.g., vaporized hydrofluoric acid).Type: GrantFiled: June 28, 2004Date of Patent: October 18, 2005Assignee: Altera CorporationInventors: William Y. Hata, Christopher J. Pass
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Patent number: 6828620Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: GrantFiled: May 12, 2003Date of Patent: December 7, 2004Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Publication number: 20030197218Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: ApplicationFiled: May 12, 2003Publication date: October 23, 2003Applicant: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6573138Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: GrantFiled: July 8, 1999Date of Patent: June 3, 2003Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6122209Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: July 8, 1999Date of Patent: September 19, 2000Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 5949710Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: October 30, 1996Date of Patent: September 7, 1999Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright