Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect, a non-volatile storage device has at least one monitor memory cell associated with a group of data memory cells. The non-volatile storage device may use different programming techniques to program the data and monitor memory cells. In one aspect, the programming technique used for the monitor memory cell is less stable with respect to state than the technique used to program the associated data memory cells. The state of the monitor memory cell may change in a predictable manner, such that the state of the monitor cell may be sensed periodically to determine whether the associated data memory cells should be refreshed.

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

Abstract: A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The energy bands of the ferroelectric layers are adjusted by providing two of the electrodes with different work functions. The difference in the work functions may be significant, such as at least 0.4-0.6 V or more. Two of the electrodes may have equal or similar work functions. For example, the work functions may be equal within a tolerance of +/?0.1 V. The memory cell can be arranged in various configurations including a FeFET (ferroelectric field effect transistor) and a FeRAM (ferroelectric random access memory). A set of memory cells can be arranged in a string such as a NAND string.

Abstract: A method is provided that includes forming a first level above a substrate, forming a second level above the first level, and forming a third level above the second level. The first level includes a plurality of first elements having a first minimum pitch, the second level includes a plurality of second elements having a second minimum pitch greater than the first minimum pitch, and the third level includes a plurality of third elements having a third minimum pitch greater than the first minimum pitch. The second elements are disposed above and aligned with a first plurality of the first elements, and the third elements are disposed above and aligned with a second plurality of the first elements.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.

Abstract: A three-dimensional resistive memory device includes an alternating stack of electrically conductive layers and insulating layers. Resistive memory elements are provided between the electrically conductive layers and a semiconductor local bit line. The semiconductor local bit line includes a heterostructure of an inner semiconductor material layer having an inner-material band gap and an outer semiconductor material layer having an outer-material band gap that is narrower than the inner-material band. A gate dielectric is located between a gate electrode and the inner semiconductor material layer.

Abstract: A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.

Abstract: A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer.

Abstract: A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

Abstract: A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2.

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.