Abstract: A microprocessor is provided which detects an escape instruction. The escape instruction indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate instruction set is encoded in the escape instruction. The subsequent instructions are routed to an execution unit or a separate processor for execution. Each instruction sequence within a program may be coded using the instruction set which most efficiently executes the function corresponding to the instruction sequence. In one embodiment, the microprocessor executes the x86 instruction set and the alternate instruction set is the ADSP 2171 instruction set. The escape instruction is defined using a previously undefined opcode within the x86 instruction set. Complex mathematical functions (which are more efficiently executed within a DSP) may be performed more efficiently than previously achievable using the x86 instruction set alone.

Abstract: A method of managing a memory array having a plurality of erasable sectors. The method initially assigns at least one of the erasable sectors as a storage array and at least one of the erasable sectors as an update array. At least one data file is then sequentially written into the storage array beginning at a starting byte within the storage array. Each data file written into the storage array is initially designated as an active file. Thereafter, one or more of the active files is deleted by re-designating an active file as a deleted file. The deletion of active files is accomplished without erasing any of the erasable sectors. In a presently preferred embodiment, the deletion of files is accomplished by setting an Active/Delete flag in a header of the file. After deleting one or more active files, the array comprises at least one active file and at least one deleted file.

Abstract: A microprocessor configured to detect subroutine call instructions having a target address indicative of a DSP function is provided. The detection of such instructions may be performed, for example, in an instruction decode unit within the microprocessor. Subroutine call instructions detected in this manner are routed to a digital signal processor coupled near the microprocessor or possibly integrated into the microprocessor. The microprocessor may be configured to store an indication that the DSP is enabled. If the DSP is not enabled, then the microprocessor executes the original routines stored at the target address of the instruction. Although the routines may not be as efficient in performing the DSP function, the program employing the function may still operate properly in the absence of the DSP. In this manner, a computer system may initially operate without the DSP included. If a user later decides to upgrade the computer system with a DSP, then the microprocessor may dispatch DSP functions to the DSP.

Abstract: A cache is provided which prefetches data words associated with a particular addressing mode. When a data word is accessed in response to the execution of an instruction, the data word is discarded by the cache. Data which is accessed in a use-once fashion (such as DSP data, for example) may be thereby available with cache-hit memory access times instead of main memory access times. The present cache prefetches data words spaced at regular or irregular intervals, wherein the interval is specified by the addressing mode of the instruction. Multiple words within a data stream may be successfully prefetched. The cache described herein may be incorporated into a microprocessor having a conventional cache as well. Data which is indicated to be used once may be stored in the present cache, while data exhibiting locality may be stored in the conventional cache. Data which exhibits locality is thereby retained within the cache system when use-once data is accessed.