Abstract: In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.

Abstract: In the broadcast video environment, it may sometimes be necessary to switch between 12G-SDI, which is a 12 Gbps interface on a single link, and quad-link 3G-SDI, which uses four 3 Gbps physical links. A routing switcher is disclosed herein that routes 12G-SDI signals between input ports and output ports. However, the apparatus also has the capability to receive quad-link 3G-SDI signals at its input ports and internally convert from quad-link 3G-SDI to 12G-SDI. The apparatus also has the capability to internally convert a 12G-SDI signal into a quad-link 3G-SDI signal for output on its output ports. Additional processing, such as link healing and/or deskewing of incoming quad-link 3G-SDI signals may be performed.

Abstract: In an FPGA device, an FPGA receiver is configured to receive a serial signal, to deserialize the received serial signal into a parallel signal, and to align parallel words in the parallel signal. Programmable FPGA fabric in the FPGA device is coupled to receive the parallel signal from the FPGA receiver. The programmable FPGA fabric is also configured to descramble data words from the parallel words in the parallel signal, to perform a phase detection operation based on the descrambled data words, to generate an alignment control signal based on the phase detection operation, and to feed back the alignment control signal to the FPGA receiver to control alignment of the parallel words in the parallel signal. The serial signal is a Serial Digital Interface (SDI) signal in an embodiment.

Abstract: In the broadcast video environment, it may sometimes be necessary to switch between 12G-SDI, which is a 12 Gbps interface on a single link, and quad-link 3G-SDI, which uses four 3 Gbps physical links. A routing switcher is disclosed herein that routes 12G-SDI signals between input ports and output ports. However, the apparatus also has the capability to receive quad-link 3G-SDI signals at its input ports and internally convert from quad-link 3G-SDI to 12G-SDI. The apparatus also has the capability to internally convert a 12G-SDI signal into a quad-link 3G-SDI signal for output on its output ports. Additional processing, such as link healing and/or deskewing of incoming quad-link 3G-SDI signals may be performed.