Patents by Inventor Christopher Kenyon
Christopher Kenyon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240115952Abstract: Methods for managing non-player characters and power centers in a computer game are based on character hierarchies and individualized correspondences between each character's traits or rank and events that involve other non-player characters or objects. Players may share power centers, character hierarchies, non-player characters, and related quests involving the shared objects with other players playing separate and unrelated game instances over a computer network, with the outcome of the quests reflected in different the games. Various configurations of game machines are used to implement the methods.Type: ApplicationFiled: May 8, 2023Publication date: April 11, 2024Inventors: Michael de Plater, Christopher Herman Hoge, Robert Kenyon Hull Roberts, Daniel Paul Valerius, Rocky Albert Newton, Kevin Leslie Stephens
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Publication number: 20240070616Abstract: A method for integrated professional network expansion during employee onboarding is implemented via a computing system including a processor. The method includes executing, via a network, an enterprise application on a first remote computing system operated by an employer associated with an enterprise, as well as causing surfacing of a professional networking UI on a display of the first remote computing system during the execution of the enterprise application. The method also includes receiving, via the professional networking UI surfaced on the display of the first remote computing system, user input including a specification of onboarding parameters for an employee of the enterprise, where the onboarding parameters correspond to one or more professional networking intentions for the employee. The method further includes causing the enterprise application to be executed on a second remote computing system operated by the employee in accordance with the specified onboarding parameters.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Choo Yei CHONG, Heidi KENYON, Neha Parikh SHAH, Deepa SHENVI PRIOLKAR, Christopher Michael DOLLAR, Jin Young KIM, Aaron Nash MELHAFF, Venkata Sreekanth KANNEPALLI, Wende E. COPFER, Harald BECKER, Amy L. HUANG
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Publication number: 20240070790Abstract: A method for data-driven professional network expansion techniques is implemented via a computing system including a processor. The method includes executing, via a network, an enterprise application on a remote computing system operated by a user associated with an enterprise and surfacing a professional networking UI on a display of the remote computing system during execution of the enterprise application. The method includes accessing enterprise-level data corresponding to the user and the enterprise, extracting parameters associated with the user and the enterprise from the enterprise-level data, and automatically generating, based on the extracted parameters, the user's professional network and a list of suggested professional contacts.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Choo Yei CHONG, Heidi KENYON, Neha Parikh SHAH, Deepa SHENVI PRIOLKAR, Christopher Michael DOLLAR, Jin Young KIM, Aaron Nash MELHAFF, Venkata Sreekanth KANNEPALLI, Wende E. COPFER, Harald BECKER, Qintian ZHANG, Amy L. HUANG
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Publication number: 20240070172Abstract: A method for friction reduction during professional network expansion is implemented via a computing system including a processor. The method includes executing, via a network, an enterprise application on a remote computing system operated by a user associated with an enterprise and surfacing a professional networking UI on a display of the remote computing system during execution of the enterprise application. The method includes generating parameters that are representative of a connection between the user and each suggested professional contact based on enterprise-level data corresponding to the user and each suggested professional contact and generating friction-reducing UI elements for each suggested professional contact based on the generated parameters.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Microsoft Technology Licensing, LLCInventors: Choo Yei CHONG, Heidi KENYON, Neha Parikh SHAH, Deepa SHENVI PRIOLKAR, Christopher Michael DOLLAR, Jin Young KIM, Aaron Nash MELHAFF, Venkata Sreekanth KANNEPALLI, Wende E. COPFER, Harald BECKER, Amy L. HUANG
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Patent number: 11688792Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.Type: GrantFiled: November 15, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon
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Publication number: 20230197826Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Christine RADLINGER, Tongtawee WACHARASINDHU, Andre BARAN, Kiran CHIKKADI, Devin MERRILL, Nilesh DENDGE, David J. TOWNER, Christopher KENYON
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Patent number: 11605632Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.Type: GrantFiled: November 17, 2021Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon, Sairam Subramanian
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Patent number: 11569370Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.Type: GrantFiled: June 27, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Leonard P. Guler, Vivek Thirtha, Shu Zhou, Nitesh Kumar, Biswajeet Guha, William Hsu, Dax Crum, Oleg Golonzka, Tahir Ghani, Christopher Kenyon
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Publication number: 20220402986Abstract: Culture media comprising manganese and methods of culturing cells to improve sialylation and glycosylation of glycoproteins are provided.Type: ApplicationFiled: August 31, 2022Publication date: December 22, 2022Inventors: Christopher Kenyon Crowell, Gustavo Enrique Grampp
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Patent number: 11329138Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.Type: GrantFiled: April 2, 2018Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Sairam Subramanian, Christopher Kenyon, Sridhar Govindaraju, Chia-Hong Jan, Mark Liu, Szuya S. Liao, Walid M. Hafez
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Publication number: 20220077302Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON
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Publication number: 20220077145Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.Type: ApplicationFiled: November 17, 2021Publication date: March 10, 2022Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
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Patent number: 11217582Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.Type: GrantFiled: March 30, 2018Date of Patent: January 4, 2022Assignee: Intel CorporationInventors: Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon, Sairam Subramanian
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Patent number: 11205708Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.Type: GrantFiled: April 2, 2018Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Sairam Subramanian, Walid M. Hafez, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert, Christopher Kenyon
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Publication number: 20210062156Abstract: This invention relates to recombinantly-expressed denosumab molecules and methods for modulating glycan profiles of denosumab molecules.Type: ApplicationFiled: April 30, 2019Publication date: March 4, 2021Applicant: Amgen Inc.Inventors: Christopher Kenyon CROWELL, Jian W U, Athena Denise NAGI, Neil KITCHEN, Alison Jean GILLESPIE, Simina Crina PETROVAN, Michael Charles BRANDENSTEIN
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Publication number: 20210047381Abstract: Culture media comprising manganese and methods of culturing cells to improve sialylation and glycosylation of glycoproteins are provided.Type: ApplicationFiled: July 24, 2020Publication date: February 18, 2021Applicant: AMGEN INC.Inventors: Christopher Kenyon Crowell, Gustavo Enrique Grampp
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Publication number: 20200411661Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Inventors: Leonard P. GULER, Vivek THIRTHA, Shu ZHOU, Nitesh KUMAR, Biswajeet GUHA, William HSU, Dax CRUM, Oleg GOLONZKA, Tahir GHANI, Christopher KENYON
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Publication number: 20190305111Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Sairam SUBRAMANIAN, Christopher KENYON, Sridhar GOVINDARAJU, Chia-Hong JAN, Mark LIU, Szuya S. LIAO, Walid M. HAFEZ
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Publication number: 20190304971Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
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Publication number: 20190305112Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.Type: ApplicationFiled: April 2, 2018Publication date: October 3, 2019Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON