Abstract: An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.

Abstract: A differential level shifter includes: a first PMOS transistor, wherein a source/drain of the first PMOS transistor is coupled to a first CMOS signal, a gate of the first PMOS transistor is coupled to ground, and another source/drain of the first PMOS transistor is coupled to a first output node; a second PMOS transistor, wherein a source/drain of the second PMOS transistor is coupled to a second CMOS signal, a gate of the second PMOS transistor is coupled to ground, and another source/drain of the second PMOS transistor is coupled to a second output node; and a shift component coupled between the first output node and the second output node.

Abstract: An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.

Abstract: An apparatus relating generally to digital-to-analog conversion is disclosed. In such an apparatus, a digital-to-analog converter (“DAC”) device includes a source DAC and a sink DAC selectively coupled to one another. The source DAC provides a first bias to the sink DAC in a sink mode, and the sink DAC provides a second bias to the source DAC in a source mode.

Abstract: A digital to analogue converter comprising at least two resistor ladders (A, B) and at least two banks of switches (SwA, SwB etc.), means for controlling said switches in accordance with at least the MSBs of a digital input signal, connecting means (Rx) for connecting the two resistor ladders at their ends to form a ring topology, said connecting means comprising means for deriving two analogue output signals to form a differential analogue output signal. The output means may include further resistance ladders and switch banks (C, D) to provide higher resolution in segmented fashion. The first and second banks of switches are on the supply side of the ladders, to avoid loading effects. Optionally each switch forms one of a matched pair of switches controlled to be closed and opened as a pair, the second switch in operation providing feedback to an amplifier (AMPA, AMPB) such that a reference voltage can be imposed on the ladder independently of the resistance of the switches.

Abstract: A digital to analogue converter comprising at least two resistor ladders (A, B) and at least two banks of switches (SwA, SwB etc.), means for controlling said switches in accordance with at least the MSBs of a digital input signal, connecting means (Rx) for connecting the two resistor ladders at their ends to form a ring topology, said connecting means comprising means for deriving two analogue output signals to form a differential analogue output signal. The output means may include further resistance ladders and switch banks (C, D) to provide higher resolution in segmented fashion. The first and second banks of switches are on the supply side of the ladders, to avoid loading effects. Optionally each switch forms one of a matched pair of switches controlled to be closed and opened as a pair, the second switch in operation providing feedback to an amplifier (AMPA, AMPB) such that a reference voltage can be imposed on the ladder independently of the resistance of the switches.