Abstract: Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

Abstract: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage.

Abstract: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.

Abstract: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes a linear receiver portion having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver portion is configured to compare the DQ signal to the reference voltage, and to generate the differential output signal in response to the comparison. A sense amplifier portion is coupled to the linear receiver portion. The sense amplifier portion has input nodes connected to the output nodes of the linear receiver portion, and an output node for a binary output signal having voltage characteristics compatible with the computer processor. The sense amplifier portion is configured to transform the differential output signal into the binary output signal.

Abstract: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage.

Abstract: Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.

Abstract: Circuitry, and an associated method, for a receiver which receives data signals transmitted upon a non-ideal transmission channel. The circuitry includes an equalizer circuit and a variable gain amplifier circuit together operable to counteract the effects of the signal degradation. Characteristics of the equalizer circuit and of the amplifier circuit are together selected responsive to detection of the signal envelope of the data signal.