Abstract: A process incudes generating, by a canary circuit of a semiconductor package, an output value. The semiconductor package includes a hardware root-of-trust engine for an electronic system. The process includes comparing, by the canary circuit, the output value to an expected value. The process incudes, responsive to a result of the comparison, regulating, by the semiconductor package, a response of the electronic system to a reset request.

Abstract: A process includes, responsive to a primary power source being enabled, receiving, from a real time clock (RTC) device of a computer platform, an indication of a first time. Responsive to the primary power source being enabled, the process includes storing first data in a first non-volatile storage of the computer platform representing a snapshot of the first time and repeatedly updating the snapshot to cause the snapshot to track the first time. Responsive to the primary power source being disabled to begin a power outage, the process includes providing, by a timer of the computer platform powered by a secondary power source, a timer output that represents an accumulated time that corresponds to the power outage. The process includes restoring a state of the RTC device responsive to the primary power source being reenabled to end the power outage.

Abstract: A process includes receiving a given reset indication to reset a semiconductor package. The given reset indication is one of a time sequence of recent indications received by the semiconductor package. The semiconductor package includes a hardware root-of-trust. The process includes detecting an activity that is associated with the semiconductor package consistent with a tampering activity. The process includes governing a response of the semiconductor package to the given reset indication responsive to the detection of the activity.

Abstract: A process includes performing actions responsive to secondary power when primary power for a computer platform is unavailable. The actions include providing, by a timer of a computer platform, a timer output that is associated with a first time domain and corresponds to an accumulated time that primary power is unavailable. Moreover, these actions include using secondary power to detect tampering with the computer platform, and responsive to detecting the tampering, reading the timer output to provide a first timestamp that represents a time of detection of the tampering. The process further includes actions which are performed responsive to primary power being subsequently available. These actions include reading data from a non-volatile storage of the computer platform. The data represents a snapshot of a real time clock (RTC) device time that is provided by an RTC device that is powered by the primary power and corresponds to a second time domain.

Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.

Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.

Abstract: A process includes controlling a current source to cause the current source to provide a plurality of different currents at different times to an output communication line of a video display interface; and acquiring a plurality of voltages corresponding to the plurality of different currents. Acquiring the plurality of voltages includes sampling a voltage of the output communication line. The process includes comparing the plurality of voltages to a plurality of voltage thresholds; and based on a result of the comparison, determining whether the video display interface is coupled to a cable-based far end termination.

Abstract: A method for assembling a computing device including initiating a board management controller of the computing device, the board management controller having at least one fuse, forming data to control a video display operatively connected to the computing device to show an image of a watermark, and modifying the computing device. The method also includes blowing the at least one fuse in response to modifying the computing device and adjusting the watermark in response to blowing the at least one fuse.

Abstract: A method for assembling a computing device including initiating a board management controller of the computing device, the board management controller having at least one fuse, forming data to control a video display operatively connected to the computing device to show an image of a watermark, and modifying the computing device. The method also includes blowing the at least one fuse in response to modifying the computing device and adjusting the watermark in response to blowing the at least one fuse.

Abstract: A process includes controlling a current source to cause the current source to provide a plurality of different currents at different times to an output communication line of a video display interface; and acquiring a plurality of voltages corresponding to the plurality of different currents. Acquiring the plurality of voltages includes sampling a voltage of the output communication line. The process includes comparing the plurality of voltages to a plurality of voltage thresholds; and based on a result of the comparison, determining whether the video display interface is coupled to a cable-based far end termination.