Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

Abstract: Techniques are provided for a fast Fourier transform (FFT) butterfly circuit. A circuit implementing the techniques according to an embodiment includes a first multiplexer configured to select a first channel or a delayed version of a second channel based on a frame index associated with the first or second channel; a second multiplexer configured to select the channel that was not selected by the first multiplexer; and a butterfly core circuit. The butterfly core circuit configured to receive a delayed version of the selected channel from the first multiplexer as a top butterfly branch; receive the selected channel from the second multiplexer as a bottom butterfly branch; apply FFT twiddle factors to the bottom butterfly branch to generate a scaled bottom butterfly branch; and generate sum and difference channel outputs of the top butterfly branch and the scaled bottom butterfly branch.

Abstract: Techniques are provided for a polyphase filtering in a dynamically reconfigurable two times (2×) oversampled channelizer. A polyphase filter implementing the techniques according to an embodiment includes a first plurality of dual port memory circuits and a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits. The polyphase filter also includes a second plurality of dual port memory circuits configured to store polyphase filter coefficients and a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. The polyphase filter further includes a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients and an adder circuit to sum the results of the multiplications to generate a filtered output.

Abstract: Techniques are provided for a fast Fourier transform (FFT) sample reorder circuit for a dynamically reconfigurable oversampled channelizer. An FFT sample reorder circuit implementing the techniques according to an embodiment includes a plurality of dual port memory circuits. The circuit also includes a first crossbar circuit configured to route input data samples to write ports of the plurality of dual port memory circuits. The circuit further includes a second crossbar circuit configured to route reordered output data samples from read ports of the plurality of dual port memory circuits to a multi-stage FFT circuit. The circuit further includes a controller circuit configured to control the routing of the input data samples and the routing of the reordered output data samples based on a selection of a stage of the multi-stage FFT circuit.

Abstract: Techniques are provided for a dynamically reconfigurable two times (2×) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2× oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2× oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.

Abstract: An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

Abstract: A system that includes a plurality of encapsulation blocks having a plurality of digital signal processing (DSP) blocks provided with preconfigured logic functions and a plurality of pacing control networks operatively connected with the plurality of DSP blocks. The system also includes a streaming cross bar operatively connected with each encapsulation block of the plurality of encapsulation blocks. Each encapsulation block of the plurality of encapsulation blocks includes a DSP block of the plurality of DSP blocks and a pacing control network of the plurality of the pacing control networks. Each DSP block of the plurality of DSP blocks is independently and separately connected with the streaming cross bar via the plurality of pacing control networks.

Abstract: An apparatus for monitoring radio frequency (RF) signals is disclosed. The apparatus includes an RF splitter, a set of track-and-hold circuits, a set of analog-to-digital circuits (ADC) and a frequency tracking module. The RF splitter splits a set of incoming RF signals into multiple RF signal paths. Each of the track-and-hold circuits, which is clocked at a different frequency than others, samples the incoming RF signals from a respective one of the RF signal paths. Each of the ADCs receives the sampled data from a respective one of the track-and-hold circuits. Each of the ADCs is also clocked at same frequency as a corresponding one of the track-and-hold circuits. The frequency tracking module determines a frequency of the incoming RF signals.

Abstract: An apparatus for monitoring radio frequency (RF) signals is disclosed. The apparatus includes an RF splitter, a set of track-and-hold circuits, a set of analog-to-digital circuits (ADC) and a frequency tracking module. The RF splitter splits a set of incoming RF signals into multiple RF signal paths. Each of the track-and-hold circuits, which is clocked at a different frequency than others, samples the incoming RF signals from a respective one of the RF signal paths. Each of the ADCs receives the sampled data from a respective one of the track-and-hold circuits. Each of the ADCs is also clocked at same frequency as a corresponding one of the track-and-hold circuits. The frequency tracking module determines a frequency of the incoming RF signals.