Abstract: A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.

Abstract: A data processing system uses alignment circuitry to align input operands in accordance with a programmable significance parameter to form aligned input operands. The aligned input operands are supplied to arithmetic circuitry, such as an integer adder or an integer multiplier, where a result value is formed. The result value is stored in an output operand storage element, such as a result register. The programmable significance parameter is independent of the result value.

Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.

Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.

Abstract: A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.

Abstract: Processing circuitry performs a plurality of lanes of processing on respective data elements of at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry identifies lane position information for each lane of processing, the lane position information for a given lane identifying a relative position of the corresponding result data element to be generated by the given lane within a corresponding result data value spanning one or more result data elements of the result vector. The processing circuitry is configured to perform each lane of processing in dependence on the lane position information identified for that lane. This enables generation of results which are wider or narrower than the vector size supported in hardware.

Abstract: A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.

Abstract: Processing circuitry 2 supports execution of program instructions having a rounding position input operand so as to generate control signals 14 for controlling processing circuitry 16 to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.

Abstract: A data processing system includes a memory controller which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.

Abstract: A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.

Abstract: A data processing system supports vector operands with components representing different bit significance portions of an integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of components comprising the vector as specified by metadata for the vector.

Abstract: A data processing system uses alignment circuitry to align input operands in accordance with a programmable significance parameter to form aligned input operands. The aligned input operands are supplied to arithmetic circuitry, such as an integer adder or an integer multiplier, where a result value is formed. The result value is stored in an output operand storage element, such as a result register. The programmable significance parameter is independent of the result value.

Abstract: An apparatus may have processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.

Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a binary value corresponding to the floating-point value.

Abstract: A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi-1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.

Abstract: A trace output unit for collecting, buffering and outputting trace data generated by trace circuitry monitoring processing activities of a data processing apparatus is described. The trace output unit comprises an input for receiving a stream of trace data; a plurality of data stores arranged in parallel with each other for storing the trace data; and storage control circuitry for controlling storage of items of the trace data in the data stores. The control circuitry is configured to route the trace items to selected ones of the data stores and to store control data identifying related trace items stored in different data stores. The trace output unit further comprises output control circuitry configured to identify related trace items stored in different data stores from the stored control data and to recombine the related trace items from different data stores to form an output trace data stream.

Abstract: A trace output unit for collecting, buffering and outputting trace data generated by trace circuitry monitoring processing activities of a data processing apparatus is described. The trace output unit comprises an input for receiving a stream of trace data; a plurality of data stores arranged in parallel with each other for storing the trace data; and storage control circuitry for controlling storage of items of the trace data in the data stores. The control circuitry is configured to route the trace items to selected ones of the data stores and to store control data identifying related trace items stored in different data stores. The trace output unit further comprises output control circuitry configured to identify related trace items stored in different data stores from the stored control data and to recombine the related trace items from different data stores to form an output trace data stream.

Abstract: A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: Xi=Xi-1*M, where Xi is an estimate of the result value for the i-th iteration of the refinement step, and M is a value determined by a portion of the refinement step. The data processing apparatus comprises a register data store having a plurality of registers operable to store data, and processing logic operable to execute instructions to perform data processing operations on data held in the register data store.