Patents by Inventor Christopher Neville
Christopher Neville has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122463Abstract: Various apparatuses are disclosed (e.g., system, device, method, or the like) for guiding the capture and assessing the quality of an image, including dental images. The apparatuses may use trained neural networks to examine images and provide users feedback regarding image quality. The neural networks may be trained based on images within image groups that have been ranked based on perceived image quality.Type: ApplicationFiled: October 16, 2023Publication date: April 18, 2024Applicant: ALIGN TECHNOLOGY, INC.Inventors: Guotu LI, Chao SHI, Chad Clayton BROWN, Christopher E. CRAMER, Phillip Thomas HARRIS, Adam SILL, Will NEVILLE, Ritvik BANSAL
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Publication number: 20120086551Abstract: A device capable of providing information to a user through a plurality of different alerting signals, includes a sensing system capable of sensing indications that the device is in a first particular physical relationship to the user's body; an alerting system capable of conveying information to the user through a plurality of different alerting signals, the alerting signals including: a first set of alerting signals and a second set of alerting signals that are such as to be less noticeable to the user if the device is in the first particular physical relationship to the user's body than the first set of alerting signals, the device further including comprising a controller responsive to the sensing system and configured to estimate from the indications whether the device is in the first particular physical relationship to the user's body, and while it is to control the alerting system so as to suppress the provision of information to the user through the second set of alerting signals.Type: ApplicationFiled: September 8, 2011Publication date: April 12, 2012Applicant: CAMBRIDGE SILICON RADIO LIMITEDInventors: Christopher Kevan Lowe, Christopher Neville Tate
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Patent number: 7313508Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.Type: GrantFiled: December 27, 2002Date of Patent: December 25, 2007Assignee: LSI CorporationInventors: Ebo Croffie, Colin Yates, Nicholas Eib, Christopher Neville, Mario Garza, Neal Callan
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Publication number: 20060281287Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.Type: ApplicationFiled: December 14, 2005Publication date: December 14, 2006Inventors: Colin Yates, Christopher Neville
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Patent number: 7001695Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.Type: GrantFiled: May 9, 2003Date of Patent: February 21, 2006Assignee: LSI Logic CorporationInventors: Ebo H. Croffie, Christopher Neville
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Publication number: 20050151949Abstract: The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a blocker to block zero order light to improve image quality for phase shift lithography systems and methodologies. A maskless lithography system is provided. The lithography system provided uses a phase shift pattern generator which projects a phase shift image pattern along an optical path onto a photoimageable layer of a substrate in order to facilitate pattern transfer. A blocking element is interposed in the optical path to block zero order light in the image pattern, thereby improving image quality.Type: ApplicationFiled: November 12, 2004Publication date: July 14, 2005Inventors: Nicholas Eib, Ebo Croffie, Christopher Neville, Neal Callan
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Publication number: 20040224239Abstract: A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.Type: ApplicationFiled: May 9, 2003Publication date: November 11, 2004Inventors: Ebo H. Croffie, Christopher Neville
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Publication number: 20040128118Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Inventors: Ebo Croffie, Colin Yates, Nicholas Eib, Christopher Neville, Mario Garza, Neal Callan
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Patent number: 6650697Abstract: To alleviate the requirement to back-off all up-link performance, such as by limiting power spectral density, to overcome far-end cross-talk problems otherwise associated with relatively short loop-length wireline links, the present invention partitions the frequency spectrum based on an estimate of the loop length of a subscriber unit (CPE) modem from an exchange (LTE) modem. Up to a threshold frequency (fmax) at which received transmissions from a subscriber having a longest loop length (115) become indistinguishable by the LTE modem from a noise floor (102), up-link performance on all loop lengths is limited to correspond to that of the longest loop. At frequencies above the threshold frequency (fmax), subsets of subscribers (152-154) having relatively short loop lengths (116-119) use high frequency carriers that have signal to noise ratios sufficient to support information transmission in these elevated frequency bands.Type: GrantFiled: July 16, 1999Date of Patent: November 18, 2003Assignee: Nortel Networks LimitedInventors: Christopher Neville Tate, Leslie Derek Humphrey, Igor Kajetan Czajkowski
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Patent number: 6577650Abstract: To facilitate acquisition of lock in a multiple sub-channel carrier scheme, a plurality of time-continuous pilots (102) on known sub-channels are made available to an addressed unit across the frequency spectrum. The addressed unit is then able to select one of these pilots for training purposes and specifically for frequency and phase acquisition (106). The selection is based, typically, on the pilot with either the best signal to noise ratio or the first pilot to satisfy the minimum quality requirements for effective training. Discontinuous carriers, of which there can be several, are then used to identify a symbol boundary at the addressed unit. Once acquisition has been established, the pilots can, if desired, be released to carry low-bit rate traffic, although it is preferable to retain pilot tones for use within the system.Type: GrantFiled: July 30, 1999Date of Patent: June 10, 2003Assignee: Nortel Networks LimitedInventors: Christopher Neville Tate, Leslie Derek Humphrey, Roger James Williamson, Igor Kajetan Czajkowski
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Patent number: 6426131Abstract: Disclosed is a pupil aperture, and method for making the pupil aperture for use in a photolithography scanner system. The pupil aperture includes a plate having a set of pole apertures that are radially offset from a reference center point of the plate. The plate further includes a horizontal reference line that intersects the reference center point. The horizontal reference line is used to define a target angle that is between about 15 degrees and about 35 degrees from the horizontal reference line. The target angle defines an off-axis location for each of the set of pole apertures. In a specific aspect of this invention, a set ranging between 3 to 9 pole apertures can be defined in the plate, and their offset from the center point can be selected to be between about 0.3 inches and about 0.9 inches.Type: GrantFiled: July 21, 1999Date of Patent: July 30, 2002Assignee: LSI Logic CorporationInventors: Philip Eric Jackson, Mario Garza, Christopher Neville
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Patent number: 6353628Abstract: To reduce power consumption and associated heating in a line card of line termination equipment (LTE, 12) employing multiple cub-channel carriers to communicate broadband information to customer premise equipment (CPE, 30) down a wireline communication resource (26, sub-channel carrier transmissions are restricted (58) during periods of CPE inactivity. Power supplies to a power amplifier (30) associated with the line card and wireline resource (26) are reduced, with digital signal processing capabilities of the LTE (12) further restricted (64). When the CPE wishes to re-start communication, the CPE (30) locks (68) to a correct alignment in a transmission scheme using a pilot tone that is transmitted within a simple pattern sent during reduced sub-channel carrier transmissions. Alternatively, should all transmission from the LTE cease during CPE inactivity, then the CPE monitors (80) the transmission environment and sends (82) a wake-up call to the LTE between boundaries of an uplink slot.Type: GrantFiled: December 15, 1998Date of Patent: March 5, 2002Assignee: Nortel Networks LimitedInventors: Andrew David Wallace, Christopher Neville Tate, Mike Francis Grant
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Patent number: 6353636Abstract: A method, and related apparatus, for determining symbol alignment in a discrete multi-tone communications system comprising the steps of: receiving a signal on each of at least one selected carrier frequency; for each of a plurality of receiver window alignments with respect to said signals, deriving a measure of received signal power level on each said selected carrier frequency; for each said receiver window alignment and selected carrier frequency deriving a measure of spectral leakage on at least one adjacent carrier frequency; selecting a receiver window alignment responsive to said derived measures.Type: GrantFiled: December 23, 1998Date of Patent: March 5, 2002Assignee: Nortel Networks LimitedInventors: Christopher Neville Tate, Andrew David Wallace, Leslie Derek Humphrey
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Patent number: 5898478Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.Type: GrantFiled: May 5, 1997Date of Patent: April 27, 1999Assignee: LSI Logic CorporationInventors: Randy Yim, Christopher Neville
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Patent number: 5627624Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.Type: GrantFiled: October 31, 1994Date of Patent: May 6, 1997Assignee: LSI Logic CorporationInventors: Randy Yim, Christopher Neville
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Patent number: 5329334Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle pattern to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.Type: GrantFiled: March 2, 1993Date of Patent: July 12, 1994Assignee: LSI Logic CorporationInventors: Randy Yim, Christopher Neville
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Patent number: RE36768Abstract: A fuel injection system for a multi-cylinder internal combustion engine, which includes a rigid elongated unitary member incorporating a gas supply duct, a fuel supply duct and a fuel return duct, each of which extends in the direction of elongation of the unitary member. A separate fuel metering device and fuel injecting device is provided for each engine cylinder. The fuel metering device is arranged to deliver metered quantities of fuel to the fuel injection device and is in communication with the fuel supply and fuel return ducts so that fuel can be circulated through each of the fuel metering devices. The fuel injecting devices are each in communication with the gas duct and communicable with one of the engine cylinders. The fuel injection devices are adapted to effect delivery of a metered quantity of fuel entrained in gas supplied from the gas duct when the fuel injecting device is in fluid communication with a cylinder.Type: GrantFiled: January 24, 1997Date of Patent: July 11, 2000Assignee: Orbital Engine Company (Australia) Pty. Ltd.Inventors: Mark Lear, Ian Reginald Thompson, Sam Russell Leighton, Christopher Neville Francis Sayer, Albert Larry Haas