Abstract: A fabrication method and resultant electronic module that facilitates relief of thermally induced stress within the module. The fabrication method includes providing a plurality of integrated circuit chips having grooves in substantially planar main surfaces thereof. The chips are stacked and bonded to each other using an expandable material and a flowable adhesive to form an electronic module. The bonding is such that movement of individual IC chips within the module, in a direction perpendicular to their planar surfaces, is restricted. Upon thermal expansion of the module, the expandable material and the individual chips expand at different rates. However, the expandable material flows into the grooves, relieving thermally induced stress.

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

Abstract: Multichip integrated circuit packages and systems of multichip packages having reduced interconnecting lead lengths are disclosed. The multichip package includes a multiplicity of semiconductor chip layers laminated together in a unitized module. A first metallization pattern is connected to the integrated circuit chips on at least one side surface of the unitized module. In addition, at least one end surface of the module contains a second metallization pattern which is configured to facilitate connection of the package to an external signal source, such as another multichip package. The system includes at least two such packages which are electrically coupled via either metallization patterns provided on the end surface of the packagers. If required, a plurality of multichip packages can be directly coupled into the system in an analogous manner. Further specific details of the multichip package and the system of multichip packages are set forth herein.

Abstract: A method of fabricating a high density electronic package is disclosed. The package includes a module of laminated semiconductor chips, including spare chip(s) and a supporting substrate with a fixed interconnect pattern. Chip connection pads are provided at a first pad level of the module; one or more pads corresponding to each chip in the module. The module is tested at the first pad level to identify defective chip(s). A spare routing pattern is applied to the module for electrically isolating defective chip(s) and effectively substituting spare chip(s) therefor such that a predetermined pattern of metal interconnect landings on an access surface of the module remains unchanged, as does the supporting substrate.

Abstract: A structure and method is disclosed for cooling a semiconductor computer chip module. The semiconductor computer chip module is made up of a plurality of semiconductor chips bonded together In one aspect of the present invention every other chip is staggered such that recesses are formed between protruding edges of every other chip along two opposite faces of the chip module. The opposite faces with the staggered chips are capped and sealed so that coolant channels are formed between the recesses and the sealing caps. In another aspect, one face of the chip module is bonded by a plurality of connectors to a base. The base and chip module with connectors form a chamber. The chamber is sealed and an opening is made in the base to circulate coolant into and around the connectors of the base and up along the coolant channels which are in fluid communication with the base. Thermal vias are provided between selected connectors and the chip module to conduct heat from the chips of the module to the connectors.

Abstract: A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.

Abstract: A redundant word decoder compares an incoming address signal with a list of defective addresses and, in response to the comparison, produces at least one comparison signal to control the propagation of a redundany driver signal along at least one redundant wordline. A main trigger receives the comparison signal and, in response thereto, controls a triggering of a main wordline driver to produce a main driver signal. The main wordline driver and the redundant word decoder are responsive to opposite states of the comparison signal, such that, for a given comparison signal, only one of the main driver signal and redundant driver signal is applied to a memory array.