Abstract: In one embodiment, an integrated circuit (IC) includes a power distribution network having a first set of power distribution lines connected to a source voltage and a second set of power distribution lines connected to a ground voltage, and a first capacitor. A first variable resistive element is electrically coupled in series with the first capacitor between the first and second sets of power lines of the power distribution network. A control circuit is coupled to the variable resistive element and is configured and arranged to adjust a level of resistance of the first variable resistive element in response to an input signal. The adjustment of the level of resistance adjusts an equivalent series resistance of the power distribution network.

Abstract: An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract: Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments of the present invention avoid impedance mismatch in circuits and achieve an advance in the art by providing a via with higher impedance through the addition of split ring resonators (SSRs) to each end of the via.

Abstract: An integrated circuit package includes a number of electrical conductors that are completely or at least partially surrounded by a gas instead of a solid material (having no cavities) used in the prior art. Such use of a gas reduces the dielectric constant in a region around each of the electrical conductors, as compared to the dielectric constant of a solid dielectric material. In one implementation, a number of leads are kept separated from a substrate by a number of electrically conductive support members attached to the substrate. Each lead is electrically coupled (e.g. by a bond wire) to a die pad on a die that is supported by the package in the normal manner. The leads are initially formed as portions of a lead frame (e.g. by etching or stamping), and are held separate from each other by the respective support members. The support members are electrically coupled (e.g. by traces and vias in the substrate) to terminals (e.g. pins, balls or lands) of the package.

Abstract: A heat sink mounted on an electronic component causes a thermal plume effect so that air adjacent to the electronic component moves through one or more channels in the heat sink in a direction substantially transverse to and away from the electronic component. The heat sink includes a base attachable to the electronic component, a support member mounted on and substantially transverse to the base, and a heat exchanger mounted on the support member and spaced away from the base. The heat exchanger has at least one entry hole adjacent to the base, at least one exit hole at a distance from the entry hole, and one or more channels adjacent to the support member and in flow communication with the entry hole and the exit hole.

Abstract: The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator includes a thermoelectric cooler used to electrically control the board simulator's thermal resistivity. The board simulator's thermal resistivity is determined in a first calibration step by measuring the difference in temperatures between two thermocouples mounted on two sides of the board simulator. Then, the board simulator is attached to a test component that includes a heating element and a temperature sensor. In a second calibration step, for a known thermal power generated by the heating element, the junction temperature of the test component is measured for different values of thermal resistivity of the board simulator. Next in a measurement step, the user determines the thermal resistivity of the target board.

Abstract: The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator's thermal resistivity is determined in a first calibration step by measuring the difference in temperatures between two thermocouples mounted on two sides of the board simulator. Then, the board simulator is attached to a test component that includes a heating element and a temperature sensor. In a second calibration step, for a known thermal power generated by the heating element, the junction temperature of the test component is measured for different values of thermal resistivity of the board simulator. Next in a measurement step, the user determines the thermal resistivity of the target board.

Abstract: The junction temperature of a die inside an electronic component is empirically determined by use of a board simulator that simulates a target board on which the electronic component is to be operated. The board simulator includes a thermoelectric cooler used to electrically control the board simulator's thermal resistivity. The board simulator's thermal resistivity is determined in a first calibration step by measuring the difference in temperatures between two thermocouples mounted on two sides of the board simulator. Then, the board simulator is attached to a test component that includes a heating element and a temperature sensor. In a second calibration step, for a known thermal power generated by the heating element, the junction temperature of the test component is measured for different values of thermal resistivity of the board simulator. Next in a measurement step, the user determines the thermal resistivity of the target board.

Abstract: A laser diode alignment package has a substrate with capacitive alignment pads. A charge generator is configured to charge or discharge each of the capacitive alignment pad to a respective voltage in response to an instruction from a processor. A laser diode chip has a conductive die paddle rigidly attached thereto and the laser diode chip is movably positioned on the substrate. The conductive die paddle is positioned with respect to the alignment pads such that when the respective voltages are applied the capacitive alignment pads, Coulomb forces will move the conductive die paddle with respect to the substrate. A feedback mechanism measures the optical power passing through the optical fiber. A processor estimates based on this measured optical power level what voltage should be applied to each of the capacitive coupling pads in order to apply Coulomb forces necessary to align the laser diode chip to the optical fiber. The processor then sends charging instructions to the charge generator.

Abstract: A heat sink mounted on an electronic component causes a thermal plume effect so that air adjacent to the electronic component moves through one or more channels in the heat sink in a direction substantially transverse to and away from the electronic component. The heat sink includes a base attachable to the electronic component, a support member mounted on and substantially transverse to the base, and a heat exchanger mounted on the support member and spaced away from the base. The heat exchanger has at least one entry hole adjacent to the base, at least one exit hole at a distance from the entry hole, and one or more channels adjacent to the support member and in flow communication with the entry hole and the exit hole.

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).

Abstract: A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground).