Patents by Inventor Christopher Petti
Christopher Petti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180197988Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.Type: ApplicationFiled: January 6, 2017Publication date: July 12, 2018Inventors: Perumal RATNAM, Christopher PETTI, Juan SAENZ, Guangle ZHOU, Abhijit BANDYOPADHYAY, Tanmay KUMAR
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Publication number: 20180182771Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leasType: ApplicationFiled: February 28, 2017Publication date: June 28, 2018Inventors: Xiying Costa, Daxin Mao, Christopher Petti, Dana Lee, Yao-Sheng Lee
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Publication number: 20180157587Abstract: A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second DNA strings, and inserting a replacement address-data block that includes a replacement data segment between the first DNA string and the second DNA string to provide a rewritten DNA strand having valid address followed by valid data and an invalid address followed by invalid data.Type: ApplicationFiled: May 25, 2017Publication date: June 7, 2018Inventors: Christopher PETTI, Srikanth RANGANATHAN
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Patent number: 9941299Abstract: A three-dimensional memory device includes an alternating stack of word lines and insulating layers, vertical semiconductor channels vertically extending through the alternating stack, and a ferroelectric memory material located between each vertical semiconductor channel and the word lines.Type: GrantFiled: May 24, 2017Date of Patent: April 10, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Yangyin Chen, Christopher Petti
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Patent number: 9922709Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.Type: GrantFiled: May 18, 2015Date of Patent: March 20, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Perumal Ratnam, Christopher Petti, Tianhong Yan
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Patent number: 9837153Abstract: Technology is described for selecting a group of reversible-resistance memory cells in which to store data based on information regarding switching the reversible-resistance memory cells from a first resistance state in which the reversible-resistance memory cells are in immediately after fabrication to a second resistance state for the first time after fabrication. Information regarding switching the reversible-resistance memory cells from the first resistance state to the second resistance state for the first time after fabrication may provide insight into factors including, but not limited to, endurance and data retention. In one aspect, a control circuit is configured to select a group of reversible-resistance memory cells in which to store data based on both the difficulty in switching from the first resistance state to the second resistance state for the first time after fabrication and a temperature of the data to be stored in the memory system.Type: GrantFiled: March 24, 2017Date of Patent: December 5, 2017Assignee: Western Digital Technologies, Inc.Inventors: Bijesh Rajamohanan, Christopher Petti, Xinde Hu
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Publication number: 20170309681Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: ApplicationFiled: June 26, 2017Publication date: October 26, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Publication number: 20170236873Abstract: Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.Type: ApplicationFiled: February 14, 2017Publication date: August 17, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Yangyin Chen, Christopher Petti
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Publication number: 20170236871Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: ApplicationFiled: March 30, 2016Publication date: August 17, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Patent number: 9735202Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: GrantFiled: March 30, 2016Date of Patent: August 15, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Patent number: 9583615Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.Type: GrantFiled: February 17, 2015Date of Patent: February 28, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yung-Tin Chen, Guangle Zhou, Christopher Petti
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Patent number: 9502471Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.Type: GrantFiled: August 25, 2015Date of Patent: November 22, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Henry Chien, Johann Alsmeier, Koji Miyata, Tong Zhang, Man Mui, James Kai, Wenguang Shi, Wei Zhao, Xiaolong Hu, Jiyin Xu, Gerrit Jan Hemink, Christopher Petti
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Patent number: 9484093Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.Type: GrantFiled: May 18, 2015Date of Patent: November 1, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Perumal Ratnam, Christopher Petti, Tianhong Yan
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Patent number: 9478495Abstract: A low-stress contact via structure for a device employing an alternating stack of insulating layers and electrically conductive layers over a substrate can be formed by forming a trench extending to the substrate through the alternating stack. After formation of an insulating spacer and a diffusion barrier layer, a remaining volume of the trench can be filled with a combination of an aluminum portion and a non-metallic material portion to form a contact via structure. The non-metallic material portion can include a semiconductor material portion or a dielectric material portion, and can prevent reflow of the aluminum portion and generation of a cavity in subsequent thermal processes. If a semiconductor material portion is employed, the aluminum portion and the semiconductor material portion can exchange places during a metal induced crystallization anneal process of the semiconductor material.Type: GrantFiled: October 26, 2015Date of Patent: October 25, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Jayavel Pachamuthu, Peter Rabkin, Jilin Xia, Christopher Petti
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Patent number: 9472758Abstract: The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.Type: GrantFiled: November 11, 2014Date of Patent: October 18, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhida Lan, Abhijit Bandyopadhyay, Christopher Petti, Li Xiao, Girish Nagavarapu
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Patent number: 9455301Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.Type: GrantFiled: May 18, 2015Date of Patent: September 27, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Perumal Ratnam, Christopher Petti, Tianhong Yan
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Publication number: 20160240665Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.Type: ApplicationFiled: February 17, 2015Publication date: August 18, 2016Inventors: Yung-Tin CHEN, Guangle Zhou, Christopher Petti
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Patent number: 9373396Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.Type: GrantFiled: May 19, 2015Date of Patent: June 21, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Perumal Ratnam, Christopher Petti, Tianhong Yan
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Publication number: 20160133836Abstract: The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.Type: ApplicationFiled: November 11, 2014Publication date: May 12, 2016Applicant: SANDISK 3D LLCInventors: Zhida Lan, Abhijit Bandyopadhyay, Christopher Petti, Li Xiao, Girish Nagavarapu
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Publication number: 20160019957Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.Type: ApplicationFiled: May 18, 2015Publication date: January 21, 2016Applicant: SANDISK 3D LLCInventors: Perumal Ratnam, Christopher Petti, Tianhong Yan