Abstract: The present disclosure provides systems and methods for transposing a cargo nucleotide sequence to a target nucleic acid site. These systems and methods may comprise a first double-stranded nucleic acid comprising the cargo nucleotide sequence, wherein the cargo nucleotide sequence is configured to interact with a retrotransposase, and the retrotransposase, wherein said retrotransposase is configured to transpose the cargo nucleotide sequence to the target nucleic acid site.

Abstract: The present disclosure provides for endonuclease enzymes having distinguishing domain features, as well as methods of using such enzymes or variants thereof.

Abstract: A fluid end comprising a plurality of fluid end sections positioned in a side-by-side relationship. Each fluid end section is releasably attached to a connect plate. Each connect plate is attached to a power source using a plurality of stay rods. Each fluid end section comprises a housing in fluid communication with a pair of intake manifolds and a discharge conduit. A fluid routing plug is installed within each housing and is configured to route fluid throughout the housing. A plunger is installed within stuffing box attached to each housing. A number of features, including the location of seals within bore walls and carbide inserts within valve guides, aid in reducing or transferring wear.

Abstract: The present disclosure provides systems and methods for transposing a cargo nucleotide sequence to a target nucleic acid site. These systems and methods may comprise a first double-stranded nucleic acid comprising the cargo nucleotide sequence, wherein the cargo nucleotide sequence is configured to interact with a transposase, and the transposase, wherein said transposase is configured to transpose the cargo nucleotide sequence to the target nucleic acid site.

Abstract: A fluid end made of a plurality of fluid end sections positioned in a side-by-side relationship. Each fluid end section is made of a housing having a discharge bore and an intake bore formed therein. A fluid routing plug is installed within each housing and is configured to route fluid throughout the housing and between the discharge and intake bores. The fluid routing plug carries seals that engage sealing surfaces formed within the housing. A number of features, including the location of seals within bore walls and carbide inserts within valve guides, aid in reducing or transferring wear within each housing.

Abstract: The present disclosure provides for endonuclease enzymes as well as methods of using such enzymes or variants thereof.

Abstract: The present disclosure provides systems and methods for transposing a cargo nucleotide sequence to a target nucleic acid site. These systems and methods can comprise a nucleic acid comprising the cargo nucleotide sequence, wherein the cargo nucleotide sequence is configured to interact with a retrotransposase, and the retrotransposase, wherein said retrotransposase is configured to transpose the cargo nucleotide sequence to the target nucleic acid site. The systems and methods can also involve use of functional fragments of retrotransposases.

Abstract: A fluid end is formed from a first body attached to a separate second body. Each body includes an external surface. When the bodies are attached, their respective external surfaces are in flush engagement. A plurality of bores are formed in the second body that are alignable with a plurality of corresponding bores formed in the first body. The fluid end may be used with seals disposed within recesses within each bore to seal against corresponding sealing surfaces. Further, retaining closures may be bolted to the fluid end bodies, such that the closures have a threadless connection to the fluid end bodies. Various combinations of such components may be utilized.

Abstract: A processor includes a processing pipeline, a plurality of result-storage elements, and writeback logic. The processing pipeline is configured to process program operations and to write, to a result storage, up to a predefined maximal number of results of the processed program operations per clock cycle. The result-storage elements are configured to store respective ones of the results. The writeback logic is configured to (i) detect a writeback conflict event in which the processing pipeline produces simultaneous results that exceed the predefined maximal number of results, for writing to the result storage, in a same clock cycle, (ii) in response to detecting the writeback conflict event, to temporarily store at least a given result, from among the simultaneous results, in a given result-storage element, and (iii) to subsequently write the temporarily-stored given result from the given result-storage element to the result storage.

Abstract: A processor includes a processing pipeline, a plurality of result-storage elements, and writeback logic. The processing pipeline is configured to process program operations and to write, to a result storage, up to a predefined maximal number of results of the processed program operations per clock cycle. The result-storage elements are configured to store respective ones of the results. The writeback logic is configured to (i) detect a writeback conflict event in which the processing pipeline produces simultaneous results that exceed the predefined maximal number of results, for writing to the result storage, in a same clock cycle, (ii) in response to detecting the writeback conflict event, to temporarily store at least a given result, from among the simultaneous results, in a given result-storage element, and (iii) to subsequently write the temporarily-stored given result from the given result-storage element to the result storage.

Abstract: In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract: An apparatus for making a crystal pre-melt includes a hermetically-sealed muffle furnace made of a non-porous refractory material, at least one port for entry and exit of gaseous substance within the muffle furnace, a temperature-controlled zone defined inside the muffle furnace, and a crucible for holding crystal raw material in solid or molten form inside the muffle furnace. The crystal pre-melt is made by disposing crystal raw material in loose powder, pressed powder, granular, or densified form in the temperature-controlled zone, heating the temperature-controlled zone to a treatment temperature that enables reaction between a fluorinating agent and oxides in the crystal raw material, reacting the fluorinating agent with the crystal raw material to produce volatile gases, removing the volatile gases from the muffle furnace, heating the crystal raw material to form a melt, and solidifying the melt to form the crystal pre-melt.

Abstract: A method of monitoring logical connections in a computer network is described. All packets exchanged via the network are intercepted and analyzed. Upon receipt of a packet, a connection management engine determines whether packet is part of an existing logical connection. If it is not, a new record is created and stored in a connection record database. Otherwise, the existing record for the logical connection in the connection record database is updated. Also described is a method of monitoring file transfers in a computer network. File transfers are monitored using an file transfer record database, which allows each packet of the file transfer to be placed in proper context. Upon interception of a packet, an application management engine (AME) first determines whether the packet is part of a file transfer. If it is not, the AME ignores the packet.

Abstract: A method of monitoring logical connections in a computer network is described. All packets exchanged via the network are intercepted and analyzed. Upon receipt of a packet, a connection management engine determines whether packet is part of an existing logical connection. If it is not, a new record is created and stored in a connection record database. Otherwise, the existing record for the logical connection in the connection record database is updated.Also described is a method of monitoring file transfers in a computer network. File transfers are monitored using an file transfer record database, which allows each packet of the file transfer to be placed in proper context. Upon interception of a packet, an application management engine (AME) first determines whether the packet is part of a file transfer. If it is not, the AME ignores the packet.