Abstract: A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Abstract: A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

Abstract: One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output voltage having a magnitude that varies based on a plurality of digital values of a digital input signal. The DAC circuit also includes a test portion configured to compare the output voltage with a predetermined test voltage for each of the plurality of digital values of the digital input signal during a test mode. The test portion can provide a digital output signal corresponding to one of acceptance and failure of the DAC circuit.

Abstract: One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output voltage having a magnitude that varies based on a plurality of digital values of a digital input signal. The DAC circuit also includes a test portion configured to compare the output voltage with a predetermined test voltage for each of the plurality of digital values of the digital input signal during a test mode. The test portion can provide a digital output signal corresponding to one of acceptance and failure of the DAC circuit.

Abstract: In one embodiment, a switching regulator comprises a control circuit that activates and deactivates at least one power switch to control a voltage of a switching node. The system also comprises an inductor that conducts a current from the switching node to an output to generate an output voltage. The system further comprises a PWM comparison circuit that controls an on-time and/or an off-time of the at least one power switch based on a comparison of a feedback voltage and a reference voltage. The PWM comparison circuit comprises a ramp signal generator configured to provide a ramp signal having a non-zero slope that is combined with either the feedback voltage or the reference voltage at a beginning of either the on-time or the off-time. The PWM comparison circuit can be further configured to set the slope of the ramp signal to zero during the off-time in a discontinuous conduction mode.

Abstract: Semiconductor devices and methods for their assembly are described in which inductor elements and additional passive or active circuit components may be combined in novel configurations. An electronic device and associated methods provide an inductor element encapsulated within a dielectric package, the inductor package having a plurality of electrical contacts on at least one surface. One or more circuit components are affixed to the package surface and operably coupled to the electrical contacts. The circuit components have a total area not larger than the inductor package surface, providing a device with overall dimensions bounded by the area of the inductor package. A preferred method embodying the invention includes a step of selecting an inductor element configuration based on performance requirements. The inductor element is packaged in a dielectric package having electrical contacts disposed on one or more surface.

Abstract: Disclosed are inductor systems with reduced volume for use in larger electronic circuits. Embodiments of the invention are disclosed for a surface mount inductor system that includes an inductor having a niche for receiving an IC component interposed between the inductor and PCB. Preferably, the assembly is encapsulated to form a complete inductor system. Also disclosed is an inductor system wherein the inductor has a niche for receiving an IC component wherein a separate mounting substrate is not required. Examples of the invention include a point load power supply.

Abstract: A switch mode power converter that limits the in-rush current at start-up and reduces the occurrence of output voltage overshoot over a range of switching frequencies. The converter includes at least one Soft-Start (SS)/Frequency-Select(FS) input, at least one oscillator enable input, and an oscillator having at least one control input. Soft-start programming is linked to the frequency selection of the converter. An external capacitor connected between the SS/FS input and ground is employed to program the soft-start time, and the switching frequency generated by the oscillator is selected via the state of the SS/FS input.

Abstract: A pulse width modulation (PWM) controller includes a shutter circuit interposed between a PWM modulator and a driver circuit. The shutter circuit receives a raw PWM output signal from the PWM modulator and processes the raw PWM signal to eliminate double pulsing that may be present on the raw PWM signal. Bypass logic responsive to a switch or software controlled enable input is provided to permit the shutter circuit to be included in the PWM controller or alternatively, to be bypassed.

Abstract: An improved method of monitoring the output power provided by a switch mode power converter that reduces the overall cost of the converter. The method includes initiating a soft-start procedure for a first output voltage in the event the first voltage channel is enabled. When the first voltage level comes within regulation, a delay counter counts a predetermined number of clock cycles. In the event a second output voltage channel is enabled between the time the first channel is enabled and the time the first voltage comes within regulation, a soft-start procedure is initiated for the second voltage and the delay counter re-starts when the second voltage comes within regulation. After the delay counter finishes counting, the first and second voltages are considered stable and a single Power-Good signal is asserted.

Abstract: An op amp clamp for charging or discharging a capacitor prevents the voltage on the capacitor from going beyond a reference voltage determined by a reference clamp voltage applied to an input of a differential amplifier. The second input of the differential amplifier is connected to the capacitor. The output of the differential amplifier is provided in a feedback loop to the capacitor. The feedback loop includes a charging circuit or a discharging circuit depending upon the function of the op amp clamp. The feedback loop may be arranged with a current mirror in which current generated by the output of the differential amplifier is mirrored in the charging or discharging circuit. A signal to activate charging or discharging is applied at the output of the differential amplifier to activate or deactivate the current mirror.