Abstract: A method, computer program product, and system for enabling the merging of a plurality of instance variables into a new composite same-class instance having the same instance variables with values determined by a user. Same-class instances are arranged in tabular format and are provided with selection buttons to allow the user to make selections of the desired instance variable values.

Abstract: A method, computer program product, and system for enabling the merging of a plurality of instance variables into a new composite same-class instance having the same instance variables with values determined by a user. Same-class instances are arranged in tabular format and are provided with selection buttons to allow the user to make selections of the desired instance variable values.

Abstract: Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: A method for checking the pattern density of a chip layout is described. Initially, the design area is subdivided into a plurality of large checking boxes. Large portions of the chip are discarded from further checking if they are found to fall within acceptable limits at the more stringent and scaled box size. The box size is successively reduced using an appropriate density for each box size until key problem areas are identified on the chip. After the check of a non-failing area, the reduction in checking box size is determined by the detected pattern density. Once the checking box size approximates that of the checking box size as dictated by the groundrule, the checking box size is fixed to that of the groundrule.

Abstract: A method is provided for fabricating a bipolar transistor in which a collector layer is formed which includes an active portion having a relatively high dopant concentration and a second portion which has a lower dopant concentration. An epitaxial intrinsic base layer is formed to overlie the collector layer in conductive communication with the active portion of the collector layer. A low-capacitance region is formed laterally adjacent to the second portion of the collector layer, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer. An emitter layer is formed to overlie the intrinsic base layer.

Abstract: A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.

Abstract: A trip unit is provided with a microcontroller and non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memory, for storing trip setting values, including initializing parameters, boot code, and operational parameters being capable of analog or digital programming depending on a switching instruction. This configuration enables one to change the trip unit's trip setting values after it is manufactured either remotely or locally. The present invention provides thus increased functionality to trip units by enabling upgrades and servicing of the trip unit by downloading replacement trip setting values to it and having multiple operational parameters (trip setting values) available.

Abstract: A trip unit is provided with a microcontroller and non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memory, for storing trip setting values, including initializing parameters, boot code, and operational parameters being capable of analog or digital programming depending on a switching instruction. This configuration enables one to change the trip unit's trip setting values after it is manufactured either remotely or locally. The present invention provides thus increased functionality to trip units by enabling upgrades and servicing of the trip unit by downloading replacement trip setting values to it and having multiple operational parameters (trip setting values) available.