Abstract: A monolithic digital chirp synthesizer (DCS) chip using GaAs/AlGaAs HI.sup.2 L technology. The 6500 HBT gate DCS chip is capable of producing linear frequency modulated (chirp) waveforms or single frequency waveforms. The major components of the DCS are two pipelined accumulators, a sine ROM, a cosine ROM and two digital to analog converters.

Abstract: A magnetic bubble memory structure having an enhanced storage density is made possible by reducing the circuit period, that is the distance between bubbles, in the storage section of the device. This reduction of the circuit period is made possible by using a gap tolerant propagation element, e.g. asymmetrical chevrons. The bubble storage sections are structured such that the areas closest to the transfer gates have a larger circuit period than the remainder of the storage section. The bubble chip architecture utilizing this means of enhancing the storage density may be of the major-minor loop configuration or the block-replicate configuration. Bubble storage sections in the form of loop structures may have a folded loop or an h loop configuration as well as a closed loop configuration. The reduction in circuit period accomplishes enhancement of the storage density without reducing the bubble diameter and other minimum circuit features to achieve this goal.