Abstract: An output driver circuit of the type having two transmission gates, which are preferably CMOS transmission gates, is improved by inserting a variable, and preferably digitally programmable, pulse stretcher in the path of both the high-enable and the low-enable signals that open and close the high-side and low-side transmission gates. The variable delay element of the pulse stretcher can be set to an optimum delay by an "empirical" procedure that entails applying a series of pulses of incrementally varying duration to the output driver circuit, while monitoring the quality of waveform that they produce. A few of these waveforms will be distorted as a result of the impedance mismatch. The variable delay element of the pulse stretcher is then repeatedly adjusted. For each value of variable delay, another series of pulses of incrementally varying duration are again applied to the output of the driver circuit while the quality of the waveforms produced is monitored.

Abstract: An active load network for a device under test includes a logic circuit for anticipating the output state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to-center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.

Abstract: A variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each transmission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.