Patents by Inventor Christopher W. Leitz
Christopher W. Leitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8436336Abstract: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.Type: GrantFiled: October 23, 2007Date of Patent: May 7, 2013Assignee: Massachusetts Institute of TechnologyInventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Patent number: 7566606Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness.Type: GrantFiled: October 6, 2006Date of Patent: July 28, 2009Assignee: AmberWave Systems CorporationInventors: Matthew T. Currie, Anthony J. Lochtefeld, Christopher W. Leitz, Eugene A. Fitzgerald
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Publication number: 20080135830Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.Type: ApplicationFiled: December 21, 2007Publication date: June 12, 2008Applicant: AmberWave Systems CorporationInventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky K. Yang, Christopher W. Leitz
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Publication number: 20080128747Abstract: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.Type: ApplicationFiled: October 23, 2007Publication date: June 5, 2008Inventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Patent number: 7332417Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.Type: GrantFiled: January 27, 2004Date of Patent: February 19, 2008Assignee: AmberWave Systems CorporationInventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky T. Yang, Christopher W. Leitz
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Patent number: 7301180Abstract: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.Type: GrantFiled: June 18, 2002Date of Patent: November 27, 2007Assignee: Massachusetts Institute of TechnologyInventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Patent number: 7141820Abstract: A structure including a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer may be formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer and/or (ii) having an average height less than 10 nm.Type: GrantFiled: February 27, 2004Date of Patent: November 28, 2006Assignee: AmberWave Systems CorporationInventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Patent number: 7138310Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness.Type: GrantFiled: June 6, 2003Date of Patent: November 21, 2006Assignee: AmberWave Systems CorporationInventors: Matthew T. Currie, Anthony J. Lochtefeld, Christopher W. Leitz, Eugene A. Fitzgerald
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Patent number: 6916727Abstract: A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.Type: GrantFiled: June 21, 2002Date of Patent: July 12, 2005Assignee: Massachusetts Institute of TechnologyInventors: Christopher W. Leitz, Minjoo L. Lee, Eugene A. Fitzgerald
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Publication number: 20040214407Abstract: Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.Type: ApplicationFiled: January 27, 2004Publication date: October 28, 2004Applicant: AmberWave Systems CorporationInventors: Richard Westhoff, Christopher J. Vineis, Matthew T. Currie, Vicky K. Yang, Christopher W. Leitz
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Publication number: 20040164318Abstract: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.Type: ApplicationFiled: February 27, 2004Publication date: August 26, 2004Applicant: Massachusetts Institute of TechnologyInventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Publication number: 20040115916Abstract: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.Type: ApplicationFiled: July 29, 2003Publication date: June 17, 2004Applicant: AmberWave Systems CorporationInventors: Anthony J. Lochtefeld, Christopher W. Leitz, Matthew T. Currie, Mayank Bulsara
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Patent number: 6730551Abstract: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.Type: GrantFiled: August 2, 2002Date of Patent: May 4, 2004Assignee: Massachusetts Institute of TechnologyInventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Publication number: 20040026765Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness.Type: ApplicationFiled: June 6, 2003Publication date: February 12, 2004Applicant: AmberWave Systems CorporationInventors: Matthew T. Currie, Anthony J. Lochtefeld, Christopher W. Leitz, Eugene A. Fitzgerald
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Publication number: 20030052334Abstract: The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.Type: ApplicationFiled: June 18, 2002Publication date: March 20, 2003Inventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Publication number: 20030025131Abstract: A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.Type: ApplicationFiled: August 2, 2002Publication date: February 6, 2003Applicant: Massachusetts Institute of TechnologyInventors: Minjoo L. Lee, Christopher W. Leitz, Eugene A. Fitzgerald
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Publication number: 20020197803Abstract: A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.Type: ApplicationFiled: June 21, 2002Publication date: December 26, 2002Applicant: AmberWave Systems CorporationInventors: Christopher W. Leitz, Minjoo L. Lee, Eugene A. Fitzgerald