Abstract: A memory interface apparatus 24 is provided with first interface circuitry 28, second interface circuitry 30 and transaction control circuitry 32. The first interface circuitry receives a first write request from a transaction master 20, 22 and issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.

Abstract: Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

Abstract: The initiator device receives requests from and issues transaction requests to a recipient device via an interconnect. A barrier generator generates barrier transaction requests indicating to the interconnect that an ordering of some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request. In response to a synchronize request querying progress of a subset of transaction requests, the initiator device actions any pending transaction requests within the subset of transaction request and the barrier generator generates and issues a barrier transaction request to the interconnect. In response to receiving a response to the barrier transaction request, the initiator device issues an acknowledge signal as a response to the synchronize request.

Abstract: A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache.

Abstract: A memory interface apparatus 24 is provided with first interface circuitry 28, second interface circuitry 30 and transaction control circuitry 32. The first interface circuitry receives a first write request from a transaction master 20, 22 and issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry.

Abstract: Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

Abstract: A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache.

Abstract: An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed.

Abstract: Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device.

Abstract: Interconnect circuitry for a data processing apparatus is disclosed.

Abstract: Interconnect circuitry for a data processing apparatus is disclosed.

Abstract: The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches.

Abstract: An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

Abstract: The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches.

Abstract: An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.